HEF4516B
Binary up/down counter
Rev. 06 — 11 December 2009
Product data sheet
1. General description
The HEF4516B is an edge-triggered synchronous 4-bit binary up/down counter with a
clock input (CP), an up/down count control input (UP/DN), an active LOW count enable
input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs
(D0 to D3), four parallel outputs (Q0 to Q3), an active LOW terminal count output (TC),
and an overriding asynchronous master reset input (MR).
Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all
other input conditions except for MR which must be LOW. When PL and CE are LOW, the
counter changes on the LOW-to-HIGH transition of CP. Input UP/DN determines the
direction of the count, counting up when HIGH and counting down when LOW. When
counting up, TC is LOW when Q0 and Q3 are HIGH and CE is LOW. When counting
down, TC is LOW when Q0 to Q3 and CE are LOW. A HIGH on MR resets the counter
(Q0 to Q3 = LOW) independent of all other input conditions.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input. It is
also suitable for use over the full industrial (−40
°C
to +85
°C)
temperature range.
2. Features
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range
−40 °C
to +85
°C
Complies with JEDEC standard JESD 13-B
3. Applications
Industrial
4. Ordering information
Table 1.
Ordering information
All types operate from
−
40
°
C to +85
°
C.
Type number
HEF4516BP
HEF4516BT
Package
Name
DIP16
SO16
Description
plastic dual in-line package; 16-leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1
NXP Semiconductors
HEF4516B
Binary up/down counter
6. Pinning information
6.1 Pinning
HEF4516B
PL
Q3
D3
D0
CE
Q0
TC
V
SS
1
2
3
4
5
6
7
8
001aae689
16 V
DD
15 CP
14 Q2
13 D2
12 D1
11 Q1
10 UP/DN
9
MR
Fig 3.
Pin configuration
6.2 Pin description
Table 2.
Symbol
PL
D0 to D3
CE
Q0 to Q3
V
SS
TC
MR
UP/DN
CP
V
DD
Pin description
Pin
1
4, 12, 13, 3
5
6, 11, 14, 2
8
7
9
10
15
16
Description
parallel load input (active HIGH)
parallel input
count enable input (active LOW)
parallel output
ground supply voltage
terminal count output (active LOW)
master reset input
up/down count control input
clock pulse input (LOW to HIGH, edge triggered)
supply voltage
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
4 of 16
NXP Semiconductors
HEF4516B
Binary up/down counter
7. Functional description
Table 3.
MR
L
L
L
L
H
[1]
Function table
[1]
PL
H
L
L
L
X
UP/DN
X
X
L
H
X
CE
X
H
L
L
X
CP
X
X
↑
↑
X
MODE
parallel load
no change
count down
count up
reset
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
↑
= positive-going transition.
CP
CE
UP/DN
MR
PL
D0
D1
D2
D3
Q0
Q1
Q2
Q3
TC
count
V
DD
V
SS
5
6
7
8
9
10
11
12
13
14
15
9
8
7
6
5
4
3
2
1
0
0
15 0
001aae693
Fig 4.
Timing diagram
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
5 of 16