Integrated
Circuit
Systems, Inc.
ICSSSTV16857
DDR 14-Bit Registered Buffer
Recommended Application:
DDR Memory Modules
Product Features:
•
Differential clock signal
•
Meets SSTL_2 signal data
•
Supports SSTL_2 class I & II specifications
•
low-voltage operation
VDD = 2.3V to 2.7V
•
48 pin TSSOP package
Pin Configuration
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK#
CLK
VDD
GND
VREF
RESET#
D8
D9
D10
D11
D12
VDD
GND
D13
D14
Truth Table
1
Inputs
RESET#
L
H
H
H
CLK
X or
Floating
↑
↑
L or H
CLK#
X or
Floating
↓
↓
L or H
D
X or
Floating
H
L
X
Q Outputs
Q
L
H
L
Q
0(2)
48-Pin TSSOP & TVSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
Notes:
1.
H = High Signal Level
L = Low Signal Level
↑
= Transition LOW-to-HIGH
↓
= Transition HIGH -to LOW
X = Irrelevant
Output level before the indicated
steady state input conditions were
established.
2.
Block Diagram
38
39
34
48
35
R
CLK
D1
CLK
CLK#
RESET#
D1
VREF
ICSSSTV16857
1
Q1
To 13 Other Channels
16857 Rev D 07/09/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICSSSTV16857
General Description
The 14-bit ICSSTV16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels
except for the RESET# input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the
positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supported with LVCMOS
levels as VREF may not be stable during power-up. RESET# is asynchronous and is intended for power-up only and
when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and
clock are switched off.
Pin Configuration
PIN NUMBER
24, 23, 20, 19, 18,
15, 14, 11, 10, 7, 6,
5, 2, 1
3, 8, 13, 22,
27, 36, 46
4, 9, 12, 16, 21
25, 26, 29, 30, 31,
32, 33, 40, 41, 42,
43, 44, 47, 48
38
39
28, 37, 45
34
35
PIN NAME
Q (14:1)
GND
VDDQ
D (14:1)
CLK
CLK#
VDD
RESET#
VREF
TYPE
OUTPUT
PWR
PWR
INPUT
INPUT
INPUT
PWR
INPUT
INPUT
Data output
Ground
Output supply voltage
Data input
Positive clock input
Negative clock input
Core supply voltage
Reset (active low)
Input reference voltage
DESCRIPTION
Third party brands and names are the property of their respective owners.
2
ICSSSTV16857
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage
1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Clamp Current . . . . . . . . . . . . . . . . . . . . . . .
Output Clamp Current . . . . . . . . . . . . . . . . . . . . .
Continuous Output Current . . . . . . . . . . . . . . . . .
VDD, VDDQ or GND Current/Pin . . . . . . . . . . . .
Package Thermal Impedance
3
....................
–65°C to +150°C
-0.5 to 3.6V
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
±50 mA
±50mA
±50mA
±100mA
55°C/W
Notes:
1. The input and output negative voltage
ratings may be excluded if the input
and output clamp ratings are observed.
2. This current will flow only whtn the
output is in the high state level
V
0
>V
DDQ
.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Recommended Operating Conditions
PARAM ETER
V
DD
V
DDQ
V
REF
V
TT
V
I
V
IH
V
IH
V
IL
V
IL
V
IH
V
IL
V
ICR
V
ID
V
IX
I
OH
I
OL
T
A
1
DESCRIPTION
Supply Voltage
I/O Supply Voltage
Reference Voltage V
REF
= 0.5X V
DDQ
Termination Voltage
Input Voltage
DC Input High Voltage
AC Input High Voltage
Data Inputs
DC Input Low Voltage
AC Input Low Voltage
Input High Voltage Level
1.7
RESET#
Input Low Voltage Level
Common mode Input Range
0.97
CLK, CLK#
Differential Input Voltage
0.36
Cross Point Voltage of Differential Clock
(V
DDQ
/2) -0.2
Pair
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
0
M IN
2.3
2.3
1.15
V
REF
-0.04
0
V
REF
+0.15
V
REF
+0.31
TYP
2.5
2.5
1.25
V
REF
M AX
2.7
2.7
1.35
V
REF
-0.04
V
DD
UNITS
V
REF
-0.15
V
REF
-0.31
0.7
1.53
(V
DDQ
/2)
+0.2
-20
20
70
V
mA
°C
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
3
ICSSSTV16857
Electrical Characteristics - DC
T
A
= 0 - 70º C; V
DD
= 2.5 V +/-200mV, V
DDQ
=2.5V 200mV; (unless otherwise stated)
SYMBOL
V
IK
V
OH
V
OL
I
I
I
DD
Operating (Static)
Dynamic operating
clock only
I
DDD
Dynamic Operating
per each data input
PARAMETERS
CONDITIONS
I
I
= -18mA
I
OH
= -100µA
I
OH
= -16mA
I
OL
= 100µA
I
OL
= 16mA
V
I
= V
DD
or GND
RESET# = GND
V
I
= V
IH (AC#)
or V
IL (AC)
,
RESET# = V
DD
RESET = V
DD
, V
I
= V
IH(AC)
or V
IL (AC)
, CK and CK#
switching 50% duty cycle.
RESET# = V
DD
, V
I
= V
IH(AC)
or V
IL (AC)
, CK and CK#
switching 50% duty cycle.
One data input switching at
half clock frequency, 50%
duty cycle
I
OH
= -20mA
I
OL
= 20mA
I
O
= 20mA, T
A
= 25° C
V
I
= V
REF
±310mV
V
ICR
= 1.25V, V
I(PP)
= 360mV
VDD
2.3V
2.3V-2.7
2.3V
2.3-2.7V
2.3V
2.7V
MIN
VDD -0.2
1.95
TYP
2.5
2
0
0.16
MAX
-1.2
UNITS
All Inputs
Standby (Static)
0.2
0.35
±5
0.01
TBD
V
µA
µA
mA
TBD
IO = 0
2.7V
TBD
µA/clock MHz
µA/ clock
MHz/data
r
OH
r
OL
r
O(∆)
C
i
Output High
Output Low
[r
OH
- r
OL
] each
separate bit
Data Inputs
CK and CK#
2.3-2.7V
2.3-2.7V
2.5V
2.5V
7
7
15
10
20
20
4
3.5
3.5
Ω
Ω
Ω
pF
2.5
2.5
Notes:
1 - Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
4
ICSSSTV16857
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
VDD=2.5±0.2V
MIN
TYP
MAX
f
clock
Clock frequency
133
200
t
PD
Clock to output time
1.1
2.4
2.8
t
RST
Reset to output time
3.1
5
t
SL
Output slew rate
1
1.5
4
2, 4
Setup time, fast slew rate
Data before CKD , CK#E
0.75
0.018
3, 4
Setup time, slow slew rate
0.9
t
SU
2,4
Hold time, fast slew rate
Data after CKD , CK#E
0.75
0.145
3, 4
Hold time, slow slew rate
T
h
0.9
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate =1V/ns.
4 - CLK, CLK# signals input slew rates are =1V/ns.
3 - For data signal input slew rate =0.5V/ns and < 1V/ns.
UNITS
MHz
ns
ns
V/ns
ns
ns
ns
ns
Sw itching Characteristics
(over recom m ended operating free-air tem perature range, unles s otherwis e noted)
SYMBOL
f
clock
t
PD
t
ph1
From
(Input)
CLK, CLK#
RESET#
To
(Output)
Q
Q
MIN
1.1
VDD=2.5±0.2V
TYP
133
2.4
3.1
UNITS
MAX
200
2.8
5
MHz
ns
ns
Third party brands and names are the property of their respective owners.
5
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