IDT82V3155PV8 datasheet, PDF - EEWORLD Datasheet

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IDT82V3155PV8: DescriptionPLL Based Clock Driver, 7 True Output(s), 5 Inverted Output(s), PDSO56, SSOP-56; Categorylogic logic; File Size384KB，30 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT82V3155PV8 Overview

PLL Based Clock Driver, 7 True Output(s), 5 Inverted Output(s), PDSO56, SSOP-56

IDT82V3155PV8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SSOP
package instruction	SSOP-56
Contacts	56
Reach Compliance Code	not_compliant
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G56
JESD-609 code	e0
length	18.415 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs	5
Number of terminals	56
Actual output times	7
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	2.794 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	7.5 mm

IDT82V3155PV8 Preview

ENHANCED T1/E1/OC3 WAN PLL

WITH DUAL REFERENCE INPUTS

FEATURES

• Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum

3, Stratum 4 Enhanced and Stratum 4 clock, OC-3 port and

155.52 Mbit/s application

• Supports ITU-T G.813 Option 1 clocks

• Supports ITU-T G.812 Type IV clocks

• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing

for E1 interface

• Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or

19.44 MHz

• Accepts two independent reference inputs which may have

same or different nominal frequencies applied to them

• Provides C1.5o,

C3o,

C2o,

C4o,

C6o, C8o,

C16o,

C19o,

C32o

and

C155 output clock signals

• Provides 7 types of 8 kHz framing pulses:

F0o,

F8o,

F16o,

F19o,

F32o,

RSP and TSP

IDT82V3155

• Provides a C2/C1.5 output clock signal with the frequency

controlled by the selected reference input Fref0 or Fref1

• Holdover frequency accuracy of 0.025 ppm

• Phase slope of 5 ns per 125 µs

• Attenuates wander from 2.1 Hz

• Fast lock mode

• Provides Time Interval Error (TIE) correction

• MTIE of 600 ns

• JTAG boundary scan

• Holdover status indication

• Freerun status indication

• Normal status indication

• Lock status indication

• Input reference quality indication

• 3.3 V operation with 5 V tolerant I/O

• Package available: 56-pin SSOP

FUNCTIONAL BLOCK DIAGRAM

TDO

TDI

OSCi

TCLR

RST

C2/C1.5

TCK

TMS

TRST

Fref0

Fref1

IN_sel

FLOCK

DPLL

JTAG

OSC

C32o

C19o

C155POS

C155NEG

TIE Control

Block

Virtual

Reference

Reference Input

Switch

C16o

C8o

C4o

C2o

C3o

C1.5o

C6o

F0o

F8o

F16o

F19o

F32o

RSP

TSP

LOCK

Frequency

Select Circuit 0

MON_out0

Reference Input

Monitor 0

Reference Input

Monitor 1

Feedback Signal

MON_out1

Invalid Input

Signal Detection

F0_sel0

F0_sel1

State Control Circuit

Frequency

Select Circuit 1

F1_sel0

F1_sel1

TIE_en MODE_sel1 MODE_sel0 Normal Holdover Freerun

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

2003

Integrated Device Technology, Inc.

OCTOBER 22, 2003

DSC-6244/1

IDT82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

INDUSTRIAL TEMPERATURE

DESCRIPTION

The IDT82V3155 is an enhanced T1/E1/OC3 WAN PLL with dual

reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which

generates low jitter ST-BUS, 19.44 MHz and 155.52 MHz clock and

framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048

MHz or 19.44 MHz input reference.

The IDT82V3155 provides 10 types of clock signals (C1.5o,

C3o,

C6o, C2o,

C4o,

C8o,

C16o,

C19o,

C32o,

C155) and 7 types of framing

signals (F0o, F8o,

F16o,

F19o,

F32o,

RSP, TSP) for multitrunk T1/E1

and STS3/OC3 links.

The IDT82V3155 is compliant with AT&T TR62411, Telcordia GR-

1244-CORE Stratum 3, Stratum 4 Enhanced, Stratum 4, OC-3 port,

155.52 Mbit/s application and ETSI ETS 300 011, ITU-T G.813 Option 1,

and ITU-T G.812 Type IV clocks. It meets the jitter/wander tolerance,

jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture

range, phase change slope, holdover frequency accuracy and MTIE

(Maximum Time Interval Error) requirements for these specifications.

The IDT82V3155 can be used in synchronization and timing control

for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse

source. It also can be used in access switch, access routers, ATM edge

switches, wireless base station controllers, or IADs (Integrated Access

Devices), PBXs, line cards and SONET/SDH equipments.

PIN CONFIGURATION

MODE_sel0

MODE_sel1

TCLR

RST

Fref0

Fref1

MON_out0

MON_out1

F0_sel0

F0_sel1

IN_sel

C6o

C1.5o

C3o

C2o

C4o

C155POS

C155NEG

C8o

C16o

C32o

TCK

TIE_en

IC2

C2/C1.5

IC0

HOLDOVER

FREERUN

OSCi

F19o

NORMAL

FLOCK

LOCK

C19o

TSP

RSP

F32o

F16o

F8o

F1_sel0

F1_sel1

F0o

TDI

TMS

TRST

TDO

IDT82V3155

Figure - 1 IDT82V3155 SSOP56 Package Pin Assignment

IDT82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

INDUSTRIAL TEMPERATURE

LIST OF TABLES

Table - 1

Table - 2

Table - 3

Table - 4

Table - 5

Operating Modes Selection ..................................................................................................................................................................9

Fref0 Frequency Selection .................................................................................................................................................................10

Fref1 Frequency Selection .................................................................................................................................................................10

Input Reference Selection ..................................................................................................................................................................11

C2/C1.5 Output Frequency Control....................................................................................................................................................14

IDT82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

INDUSTRIAL TEMPERATURE

LIST OF FIGURES

Figure - 1

Figure - 2

Figure - 3

Figure - 4

Figure - 5

Figure - 6

Figure - 7

Figure - 8

Figure - 9

Figure - 10

Figure - 11

Figure - 12

Figure - 13

Figure - 14

IDT82V3155 SSOP56 Package Pin Assignment ................................................................................................................................ 2

State Control Circuit ............................................................................................................................................................................ 9

State Control Diagram......................................................................................................................................................................... 9

TIE Control Block Diagram................................................................................................................................................................ 11

Reference Switch with TIE Control Block Enabled............................................................................................................................ 12

Reference Switch with TIE Control Block Disabled........................................................................................................................... 12

DPLL Block Diagram ......................................................................................................................................................................... 13

Clock Oscillator Circuit ...................................................................................................................................................................... 14

Power-Up Reset Circuit..................................................................................................................................................................... 14

Timing Parameter Measurement Voltage Levels .............................................................................................................................. 25

Input to Output Timing (Normal Mode).............................................................................................................................................. 27

Output Timing 1................................................................................................................................................................................. 28

Output Timing 2................................................................................................................................................................................. 29

Input Control Setup and Hold Timing ................................................................................................................................................ 29

IDT82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

INDUSTRIAL TEMPERATURE

TABLE OF CONTENTS

Pin Description...................................................................................................................................................................................................7

Functional Description ......................................................................................................................................................................................9

2.1 State Control Circuit ..................................................................................................................................................................................9

2.1.1 Normal Mode..............................................................................................................................................................................10

2.1.2 Fast Lock Mode..........................................................................................................................................................................10

2.1.3 Holdover Mode ...........................................................................................................................................................................10

2.1.4 Freerun Mode.............................................................................................................................................................................10

2.2 Frequency Select Circuit .........................................................................................................................................................................10

2.3 Reference Input Switch ...........................................................................................................................................................................11

2.4 Reference Input Monitor ..........................................................................................................................................................................11

2.5 Invalid Input Signal Detection ..................................................................................................................................................................11

2.6 TIE Control Block.....................................................................................................................................................................................11

2.7 DPLL Block..............................................................................................................................................................................................12

2.7.1 Phase Detector (PHD)................................................................................................................................................................12

2.7.2 Limiter.........................................................................................................................................................................................13

2.7.3 Loop Filter ..................................................................................................................................................................................13

2.7.4 Fraction Block.............................................................................................................................................................................13

2.7.5 Digital Control Oscillator (DCO)..................................................................................................................................................13

2.7.6 Lock Indicator .............................................................................................................................................................................14

2.7.7 Output Interface..........................................................................................................................................................................14

2.8 OSC.........................................................................................................................................................................................................14

2.8.1 Clock Oscillator ..........................................................................................................................................................................14

2.9 JTAG .......................................................................................................................................................................................................14

2.10 Reset Circuit ............................................................................................................................................................................................14

Measures of Performance ...............................................................................................................................................................................15

3.1 Intrinsic Jitter ...........................................................................................................................................................................................15

3.2 Jitter Tolerance........................................................................................................................................................................................15

3.3 Jitter Transfer ..........................................................................................................................................................................................15

3.4 Frequency Accuracy................................................................................................................................................................................15

3.5 Holdover Accuracy ..................................................................................................................................................................................15

3.6 Capture Range ........................................................................................................................................................................................15

3.7 Lock Range .............................................................................................................................................................................................15

3.8 Phase Slope ............................................................................................................................................................................................15

3.9 Time Interval Error (TIE)..........................................................................................................................................................................15

3.10 Maximum Time Interval Error (MTIE) ......................................................................................................................................................15

3.11 Phase Continuity .....................................................................................................................................................................................16

3.12 Phase Lock Time.....................................................................................................................................................................................16

Absolute Maximum Ratings ............................................................................................................................................................................17

Recommended DC Operating Conditions .....................................................................................................................................................17

DC Electrical Characteristics ..........................................................................................................................................................................17

6.1 Single End Input/Output Port...................................................................................................................................................................17

6.2 Differential Output Port (LVDS) ...............................................................................................................................................................18

AC Electrical Characteristics .........................................................................................................................................................................19

7.1 Performance ............................................................................................................................................................................................19

7.2 Intrinsic Jitter Unfiltered ...........................................................................................................................................................................20

7.3 C1.5o (1.544 MHz) Intrinsic Jitter Filtered ...............................................................................................................................................20

7.4 C2o (2.048 MHz) Intrinsic Jitter Filtered ..................................................................................................................................................20

7.5 C19o (19.44 MHz) Intrinsic Jitter Filtered ................................................................................................................................................20

7.6 C155 (155.52 MHz) Intrinsic Jitter Filtered ..............................................................................................................................................21

7.7 8 kHz Input to 8 kHz Output Jitter Transfer .............................................................................................................................................21

7.8 1.544 MHz Input to 1.544 MHz Output Jitter Transfer.............................................................................................................................21

7.9 2.048 MHz Input to 2.048 MHz Output Jitter Transfer.............................................................................................................................22

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