CY7C385P-0JC datasheet, PDF - EEWORLD Datasheet

CY7C385P-0JC: DescriptionField Programmable Gate Array, 384 CLBs, 4000 Gates, 208.1MHz, 384-Cell, CMOS, PQCC84, PLASTIC, LCC-84; CategoryProgrammable logic devices Programmable logic; File Size318KB，12 Pages; ManufacturerCypress Semiconductor

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CY7C385P-0JC Overview

Field Programmable Gate Array, 384 CLBs, 4000 Gates, 208.1MHz, 384-Cell, CMOS, PQCC84, PLASTIC, LCC-84

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	LCC
package instruction	PLASTIC, LCC-84
Contacts	84
Reach Compliance Code	not_compliant
Other features	MAX 68 I/OS; OTP BASED
maximum clock frequency	208.1 MHz
Combined latency of CLB-Max	8.215 ns
JESD-30 code	S-PQCC-J84
JESD-609 code	e0
length	29.3116 mm
Configurable number of logic blocks	384
Equivalent number of gates	4000
Number of entries	76
Number of logical units	384
Output times	68
Number of terminals	84
Maximum operating temperature	70 °C
Minimum operating temperature
organize	384 CLBS, 4000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC84,1.2SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	29.3116 mm

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