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MC74HCT138A
1-of-8 Decoder/
Demultiplexer with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT138A is identical in pinout to the LS138. The
HCT138A may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
The HCT138A decodes a three−bit Address to one−of−eight
active−lot outputs. This device features three Chip Select inputs, two
active−low and one active−high to facilitate the demultiplexing,
cascading, and chip−selecting functions. The demultiplexing function
is accomplished by using the Address inputs to select the desired
device output; one of the Chip Selects is used as a data input while the
other Chip Selects are held in their active states.
Features
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MARKING
DIAGRAMS
16
16
1
PDIP−16
N SUFFIX
CASE 648
MC74HCT138AN
AWLYYWWG
1
16
16
1
SOIC−16
D SUFFIX
CASE 751B
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
HCT
138A
ALYWG
G
HCT138AG
AWLYWW
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
mA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
•
Chip Complexity: 122 FETs or 30.5 Equivalent Gates
•
Pb−Free Packages are Available*
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2009
December, 2009
−
Rev. 9
1
Publication Order Number:
MC74HCT138A/D
MC74HCT138A
LOGIC DIAGRAM
A0
ADDRESS
INPUTS
A1
A2
1
2
3
15
14
13
12
11
10
9
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
ACTIVE-LOW
OUTPUTS
PIN ASSIGNMENT
A0
A1
A2
CS2
CS3
CS1
Y7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
CHIP-
SELECT
INPUTS
CS1
CS2
CS3
6
4
5
PIN 16 = V
CC
PIN 8 = GND
GND
FUNCTION TABLE
Inputs
X
X
L
H
H
H
H
H
H
H
H
X
H
X
L
L
L
L
L
L
L
L
H
X
X
L
L
L
L
L
L
L
L
X
X
X
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
X
X
X
L
H
L
H
L
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
Outputs
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
ORDERING INFORMATION
Device
MC74HCT138ANG
MC74HCT138ADG
MC74HCT138ADR2G
MC74HCT138ADTR2
Package
PDIP−16
(Pb−Free)
SOIC−16
(Pb−Free)
SOIC−16
(Pb−Free)
TSSOP−16*
Shipping
†
500 Units / Box
48 Units / Rail
2500 Units / Tape & Reel
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Design Criteria
Value
30.5
1.5
5.0
Units
ea.
ns
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
mW
pJ
.0075
*Equivalent to a two−input NAND gate.
2
H = high level (steady state)
L = low level (steady state)
X = don’t care
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MC74HCT138A
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
in
I
out
I
CC
P
D
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
TSSOP Package†
Value
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
– 0.5 to V
CC
+ 0.5
±
20
±
25
±
50
750
500
450
– 65 to + 150
260
Unit
V
V
V
mA
mA
mA
mW
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
T
stg
T
L
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, TSSOP or SOIC Package)
_C
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package:
−
6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min
4.5
0
– 55
0
Max
5.5
V
CC
+ 125
500
Unit
V
V
_C
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High−Level Input
Voltage
Maximum Low−Level Input
Voltage
Minimum High−Level Output
Voltage
Test Conditions
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
|I
out
|
v
4.0 mA
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
|I
out
|
v
4.0 mA
I
in
I
CC
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
Additional Quiescent Supply
Current
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
V
in
= 2.4 V, Any One Input
V
in
= V
CC
or GND, Other Inputs
l
out
= 0
mA
V
CC
V
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
6.0
5.5
– 55 to
25_C
2.0
2.0
0.8
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±
0.1
4.0
≥
−
55_C
5.5
2.9
v
85_C
2.0
2.0
0.8
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±
1.0
40
v
125_C
2.0
2.0
0.8
0.8
4.4
5.4
3.7
0.1
0.1
0.4
±
1.0
160
mA
mA
V
Unit
V
V
V
25_C to 125_C
2.4
mA
DI
CC
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3
MC74HCT138A
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0 V
±
10%, C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
t
PLH
,
t
PHL
t
PLH
,
t
PHL
t
TLH
,
t
THL
t
r
, t
f
C
in
Parameter
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 4)
Maximum Propagation Delay, CS1 to Output Y
(Figures 2 and 4)
Maximum Output Transition Time, CS2 or CS3 to Output Y
(Figures 3 and 4)
Maximum Output Transition Time, Any Output
(Figures 2 and 4)
Maximum Input Rise and Fall Time
Maximum Input Capacitance
– 55 to
25_C
30
27
30
15
500
10
v
85_C
38
34
38
19
500
10
v
125_C
45
41
45
22
500
10
Unit
ns
ns
ns
ns
ns
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
51
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC 2
f + I
CC
V
CC
.
EXPANDED LOGIC DIAGRAM
15
Y0
14
Y1
A0
1
13
Y2
A1
2
12
Y3
11
A2
3
10
CS3
CS2
5
4
9
Y4
Y5
Y6
7
Y7
CS1
6
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4
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