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Datasheet> All Categories > Discrete semiconductor> The transistor> UPA1764G-A
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UPA1764G-A

Description
Power Field-Effect Transistor, 7A I(D), 60V, 0.046ohm, 2-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, POWER, SOP-8
CategoryDiscrete semiconductor    The transistor   
File Size71KB，8 Pages
ManufacturerNEC Electronics
Download Datasheet Parametric View All

UPA1764G-A Overview

Power Field-Effect Transistor, 7A I(D), 60V, 0.046ohm, 2-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, POWER, SOP-8

UPA1764G-A Parametric

Parameter NameAttribute value
MakerNEC Electronics
Parts packaging codeSOT
package instructionSMALL OUTLINE, R-PDSO-G8
Contacts8
Reach Compliance Codeunknown
ECCN codeEAR99
Avalanche Energy Efficiency Rating (Eas)98 mJ
ConfigurationSEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage60 V
Maximum drain current (ID)7 A
Maximum drain-source on-resistance0.046 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G8
JESD-609 codee6
Number of components2
Number of terminals8
Operating modeENHANCEMENT MODE
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum pulsed drain current (IDM)28 A
Certification statusNot Qualified
surface mountYES
Terminal surfaceTIN BISMUTH
Terminal formGULL WING
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON

UPA1764G-A Preview

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA1764
SWITCHING
DUAL N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
The
µ
PA1764 is N-Channel MOS Field Effect Transistor
designed for high current switching applications.
PACKAGE DRAWING (Unit : mm)
8
5
1 : Source 1
2 : Gate 1
7, 8 : Drain 1
3 : Source 2
4 : Gate 2
5, 6 : Drain 2
6.0 ±0.3
4.4
+0.10
–0.05
FEATURES
•
Dual chip type
•
Low on-state resistance
R
DS(on)1
= 27 mΩ TYP. (V
GS
= 10 V, I
D
= 3.5 A)
R
DS(on)2
= 32 mΩ TYP. (V
GS
= 4.5 V, I
D
= 3.5 A)
R
DS(on)3
= 34 mΩ TYP. (V
GS
= 4.0 V, I
D
= 3.5 A)
•
Low input capacitance
C
iss
= 1300 pF TYP.
•
Built-in G-S protection diode
•
Small and surface mount package (Power SOP8)
1
4
5.37 MAX.
1.44
0.8
1.8 MAX.
0.15
0.05 MIN.
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power SOP8
µ
PA1764G
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC) (T
C
= 25°C)
Drain Current (pulse)
Note1
Note2
Note2
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
P
T
T
ch
T
stg
60
±20
±7
±28
1.7
2.0
150
–55 to + 150
7
98
V
V
A
A
W
W
°C
°C
A
mJ
Gate
Body
Diode
EQUIVALENT CIRCUIT
(1/2 Circuit)
Drain
Total Power Dissipation (1 unit)
Total Power Dissipation (2 unit)
Channel Temperature
Storage Temperature
Single Avalanche Current
Single Avalanche Energy
Notes 1.
2.
3.
Remark
Note3
Note3
I
AS
E
AS
PW
≤
10
µ
s, Duty cycle
≤
1%
2
T
A
= 25°C, Mounted on ceramic substrate of 1200 mm x 2.2 mm
Starting T
ch
= 25°C, V
DD
= 30 V, R
G
= 25
Ω,
V
GS
= 20
→
0 V
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
Gate
Protection
Diode
Source
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G14329EJ2V0DS00 (2nd edition)
Date Published May 2001 NS CP(K)
Printed in Japan
The mark
5
shows major revised points.
©
1999, 2001
µ
PA1764
ELECTRICAL CHARACTERISTICS (T
A
= 25°C, All terminals are connected.)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate Cut-off Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
SYMBOL
I
DSS
I
GSS
V
GS(off)
| y
fs
|
R
DS(on)1
R
DS(on)2
R
DS(on)3
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GS
Q
GD
V
F(S-D)
t
rr
Q
rr
V
DD
= 48 V
V
GS
= 10 V
I
D
= 7.0 A
I
F
= 7.0 A, V
GS
= 0 V
I
F
= 7.0 A, V
GS
= 0 V
di/dt = 100 A/
µ
s
TEST CONDITIONS
V
DS
= 60 V, V
GS
= 0 V
V
GS
= ±20 V, V
DS
= 0 V
V
DS
= 10 V, I
D
= 1 mA
V
DS
= 10 V, I
D
= 3.5 A
V
GS
= 10 V, I
D
= 3.5 A
V
GS
= 4.5 V, I
D
= 3.5 A
V
GS
= 4.0 V, I
D
= 3.5 A
V
DS
= 10 V
V
GS
= 0 V
f = 1 MHz
V
DD
= 30 V, I
D
= 3.5 A
V
GS
= 10 V
R
G
= 10
Ω
1.5
5.0
2.0
9.0
27
32
34
1300
230
110
15
69
65
27
29
3.6
7.4
0.84
40
66
35
42
46
MIN.
TYP.
MAX.
10
±10
2.5
UNIT
µ
A
µ
A
V
S
mΩ
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
R
G
= 25
Ω
PG.
V
GS
= 20
→
0 V
BV
DSS
V
DS
V
GS
0
50
Ω
L
V
DD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
R
L
PG.
R
G
V
DD
I
D
90%
90%
V
GS
V
GS
Wave Form
90%
0
10%
I
AS
I
D
V
DD
I
D
I
D
Wave Form
0 10%
10%
τ
τ
= 1
µ
s
Duty Cycle
≤
1%
t
d(on)
t
on
t
r
t
d(off)
t
off
t
f
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
= 2 mA
50
Ω
R
L
V
DD
PG.
2
Data Sheet G14329EJ2V0DS
µ
PA1764
TYPICAL CHARACTERISTICS (T
A
= 25°C, All terminals are connected.)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
P
T
- Total Power Dissipation - W/package
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
20
40
60
80
2 unit
1 unit
dT - Percentage of Rated Power - %
100
80
60
40
20
Mounted on ceramic
substrate
2
of
1200 mm
×
2.2 mm
0
20
40
60
80
100 120 140 160
100 120 140 160
T
A
- Ambient Temperature - ˚C
T
A
- Ambient Temperature - ˚C
5
100
FORWARD BIAS SAFE OPERATING AREA
d
ite )
Lim 10 V
)
on
=
S(
R
D
V
GS
t
I
D(DC)
(a
DC
Po
we
r
10
Di
ss
PW
I
D
- Drain Current - A
10
1m
10
0m
=1
s
00
µ
s
ms
s
1
ipa
tio
nL
im
0.1
ite
d
Remark
Mounted on ceramic substrate of
1200 mm
×
2.2 mm
2
0.01
0.1
T
A
= 25˚C
Single Pulse
1
10
100
V
DS
- Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
r
th(t)
- Transient Thermal Resistance - ˚C/W
1000
100
R
th
(ch-A)
= 73.5˚C/W
10
1.0
Mounted on ceramic
substrate of 1200 mm
2
×
2.2 mm
Single pulse, 1 unit
T
A
= 25˚C
0.1
100
µ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
Data Sheet G14329EJ2V0DS
3
µ
PA1764
FORWARD TRANSFER CHARACTERISTICS
100
Pulsed
V
DS
= 10 V
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
35
Pulsed
30
I
D
- Drain Current - A
I
D
- Drain Current - A
10
T
A
= 150˚C
T
A
= 75˚C
25
20
15
10
5
V
GS
= 10 V
1
T
A
= 25˚C
T
A
=
−25˚C
V
GS
= 4.5 V
V
GS
= 4.0 V
0.1
0.01
1
2
3
4
5
6
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
V
GS
-
Gate to Source Voltage - V
V
DS
- Drain to Source Voltage - V
|y
fs
| - Forward Transfer Admittance - S
100
T
A
=
−25˚C
10
T
A
= 25˚C
V
DS
= 10 V
Pulsed
R
DS(on)
- Drain to Source On-state Resistance - mΩ
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
100
Pulsed
80
60
1
T
A
= 150˚C
0.1
T
A
= 75˚C
40
I
D
= 7 A
20
0.01
0.01
0.1
1
10
100
0
0
5
10
15
I
D
- Drain Current - A
V
GS
- Gate to Source Voltage - V
R
DS(on)
- Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
100
90
80
70
60
50
40
30
20
10
0
0.1
1
10
100
V
GS
= 10 V
V
GS
= 4.0 V
V
GS
= 4.5 V
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
V
GS(off)
- Gate to Source Cut-off Voltage - V
Pulsed
3
2.5
2
1.5
1
0.5
0
V
DS
= 10 V
I
D
= 1 mA
−
50
0
50
100
150
I
D
- Drain Current - A
T
ch
- Channel Temperature - ˚C
4
Data Sheet G14329EJ2V0DS
µ
PA1764
R
DS(on)
- Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
100
Pulsed
80
V
GS
= 4.0 V
V
GS
= 4.5 V
V
GS
= 10 V
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
100
Pulsed
I
F
- Diode Forward Current - A
10
V
GS
= 4.5 V
1
V
GS
= 0 V
60
40
20
I
D
= 3.5 A
−
50
0
50
100
150
0.1
0
0.01
0
0.5
1.0
1.5
V
SD
- Source to Drain Voltage - V
T
ch
- Channel Temperature - ˚C
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
10000
SWITCHING CHARACTERISTICS
1000
t
d(on)
, t
r
, t
d(off)
, t
f
- Switching Time - ns
C
iss
, C
oss
, C
rss
- Capacitance - pF
V
GS
= 0 V
f = 1 MHz
C
iss
t
r
t
d(off)
t
f
10
t
d(on)
1000
C
oss
100
100
C
rss
1
0.1
1
10
100
1
0.1
V
DS
= 30 V
V
GS
= 10 V
R
G
= 10
Ω
1
10
100
V
DS
- Drain to Source Voltage - V
I
D
- Drain Current - A
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
V
DS
- Drain to Source Voltage - V
t
rr
- Reverse Recovery Time - ns
di/dt = 100 A/µs
V
GS
= 0 V
50
40
30
20
10
0
0
V
DD
= 48 V
30 V
12 V
V
GS
10
8
6
4
2
100
10
V
DS
I
D
= 7 A
8
16
24
32
40
1
0.1
0
1
10
100
I
D
- Drain Current - A
Q
G
- Gate Charge - nC
Data Sheet G14329EJ2V0DS
V
GS
- Gate to Source Voltage - V
1000
60
12
5
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