ASAHI KASEI
[AK4395]
Advanced Multi-Bit 192kHz 24-Bit
∆Σ
DAC
GENERAL DESCRIPTION
The AK4395 is a high performance stereo DAC for the 192kHz sampling mode of DVD-Audio including a
24bit digital filter. The digital filter has high stopband attenuation with 110dB or more that reduces wide
band aliasing noise. The AK4395 introduces the advanced multi-bit system for
∆Σ
modulator. This new
architecture achieves the wider dynamic range, while keeping much the same superior distortion
characteristics as conventional Single-Bit way. The analog outputs are filtered in the analog domain by
switched-capacitor filter (SCF) with high tolerance to clock jitter. The AK4395 also includes digital
volume, so the device is suitable for multi-channel audio system.
FEATURES
•
128x Oversampling
•
Sampling Rate up to 192kHz
•
High Performance 24Bit 8x Digital Filter (Slow Roll-off Option)
Ripple:
±0.0002dB,
Attenuation: 110dB
•
High Tolerance to Clock Jitter
•
Low Distortion Differential Output
•
Digital de-emphasis for 32, 44.1 & 48kHz sampling
•
Channel Independent Digital Volume with Soft-transition
•
Soft Mute
•
THD+N: -100dB
•
DR, S/N: 120dB
•
I/F format:
MSB justified, 16/20/24bit LSB justified, I
2
S
•
Master Clock: Normal Speed: 256fs, 384fs, 512fs or 768fs
Double Speed: 128fs, 192fs, 256fs or 384fs
Quad Speed: 128fs or 192fs
•
Power Supply: 5V±5%
•
TTL Level Digital I/F
•
Small Package: 28pin VSOP
•
Pin Compatible with AK4393/4
DIF0
DIF1
DIF2
DVDD
DVSS
DEM0
DEM1
AVDD AVSS
AK4395
LRCK
BICK
SDATA
Audio Data
Interface
De-emphasis
DATT, Soft Mute
De-emphasis
DATT, Soft Mute
Control Register
8x
Interpolator
8x
Interpolator
De-emphasis
Control
∆Σ
Modulator
∆Σ
Modulator
BVSS
VCOM
DZFL
AOUTL+
SMUTE
SCF
AOUTL-
AOUTR+
SCF
PDN
CAD0
CAD1
AOUTR-
DZFR
Clock Divider
CSN
CCLK
CDTI
P/S
MCLK
VREFH VREFL
MS0040-E-01
-1-
2001/4
ASAHI KASEI
[AK4395]
Ordering Guide
AK4395VF
AKD4395
-10 ~ +70
°C
28pin VSOP (0.65mm pitch)
Evaluation Board
Pin Layout
DVSS
DVDD
MCLK
PDN
BICK
SDATA
LRCK
SMUTE/CSN
DFS0/CAD0
DEM0/CCLK
DEM1/CDTI
DIF0
DIF1
DIF2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
ACKS/DZFR
CKS1/CAD1
CKS0/DZFL
P/S
VCOM
AOUTL
+
AOUTL-
AOUTR+
AOUTR-
AVSS
AVDD
VREFH
VREFL
BVSS
Top
View
23
22
21
20
19
18
17
16
15
Compatibility with AK4393/4
AK4395
fs (max)
DVDD
Digital Filter Stopband Attenuation
Digital Volume
µP
I/F Address Pin
De-emphasis filter
Optional Filter
Zero Detection Pin
216kHz
4.75~5.25V
110dB
256 levels, 0.5dB
CAD0/CAD1
32k,44.1k,48k
Slow Roll-off
DZFL/DZFR
AK4394
216kHz
4.75~5.25V
75dB
N/A
N/A
32k,44.1k,48k,96k
Slow Roll-off
DZFL/DZFR
AK4393
108kHz
3~5.25V
75dB
N/A
N/A
32k,44.1k,48k,96k
N/A
N/A
MS0040-E-01
-2-
2001/4
ASAHI KASEI
[AK4395]
PIN/FUNCTION
No.
1
2
3
4
BICK
SDATA
LRCK
SMUTE
I
I
I
I
Pin Name
DVSS
DVDD
MCLK
PDN
I/O
-
-
I
I
Function
Digital Ground Pin
Digital Power Supply Pin, 5.0V
Master Clock Input Pin
Power-Down Mode Pin
When at “L”, the AK4395 is in power-down mode and is held in reset.
The AK4395 should always be reset upon power-up.
Audio Serial Data Clock Pin
The clock of 64fs or more than is recommended to be input on this pin.
Audio Serial Data Input Pin
2’s complement MSB-first data is input on this pin.
L/R Clock Pin
Soft Mute Pin in parallel mode
When this pin goes “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
Chip Select Pin in serial mode
Sampling Speed Mode Select Pin in parallel mode (Internal pull-down pin)
“L”: Normal Speed, “H”: Double Speed
Chip Address 0 Pin in serial mode
(Internal pull-down pin)
De-emphasis Enable Pin in parallel mode
Control Data Clock Pin in serial mode
De-emphasis Enable Pin in parallel mode
Control Data Input Pin in serial mode
Digital Input Format Pin
Digital Input Format Pin
Digital Input Format Pin
Substrate Ground Pin, 0V
Low Level Voltage Reference Input Pin
High Level Voltage Reference Input Pin
Analog Power Supply Pin, 5.0V
Analog Ground Pin, 0V
Rch Negative analog output Pin
Rch Positive analog output Pin
Lch Negative analog output Pin
Lch Positive analog output Pin
Common Voltage Output Pin, 2.6V
Parallel/Serial Select Pin
(Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
Master Clock Select Pin in parallel mode
Lch Zero Input Detect Pin in serial mode
Master Clock Select Pin in parallel mode
(Internal pull-down pin)
Chip Address 1 Pin in serial mode
(Internal pull-down pin)
Master Clock Auto Setting Mode Pin in parallel mode
Rch Zero Input Detect Pin in serial mode
5
6
7
8
CSN
DFS0
9
CAD0
DEM0
CCLK
DEM1
CDTI
DIF0
DIF1
DIF2
BVSS
VREFL
VREFH
AVDD
AVSS
AOUTR-
AOUTR+
AOUTL-
AOUTL+
VCOM
P/S
CKS0
DZFL
CKS1
CAD1
ACKS
DZFR
I
I
I
I
I
I
I
I
-
I
I
-
-
O
O
O
O
O
I
I
O
I
I
I
O
I
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Note: All input pins except internal pull-up/down pins should not be left floating.
MS0040-E-01
-3-
2001/4
ASAHI KASEI
[AK4395]
ABSOLUTE MAXIMUM RATINGS
(AVSS, BVSS, DVSS = 0V; Note 1)
Parameter
Symbol
min
Power Supplies:
Analog
AVDD
-0.3
Digital
DVDD
-0.3
| BVSS-DVSS |
(Note 2)
-
∆
GND
Input Current , Any pin Except Supplies
IIN
-
Input Voltage
VIND
-0.3
Ambient Operating Temperature
Ta
-10
Storage Temperature
Tstg
-65
Notes: 1. All voltages with respect to ground.
2. AVSS, BVSS and DVSS must be connected to the same analog ground plane.
max
6.0
6.0
0.3
±10
DVDD+0.3
70
150
Units
V
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, BVSS, DVSS=0V; Note 1)
Parameter
Symbol
min
typ
Power Supplies:
Analog
AVDD
4.75
5.0
(Note 3)
Digital
DVDD
4.75
5.0
Voltage Reference
“H” voltage reference
VREFH
AVDD-0.5
-
(Note 4)
“L” voltage reference
VREFL
AVSS
-
VREFH-VREFL
3.0
-
∆
VREF
Notes: 3. The power up sequence between AVDD and DVDD is not critical.
4. Analog output voltage scales with the voltage of (VREFH-VREFL).
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) =
±2.4Vpp×(VREFH-VREFL)/5.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
max
5.25
5.25
AVDD
-
AVDD
Units
V
V
V
V
V
MS0040-E-01
-4-
2001/4
ASAHI KASEI
[AK4395]
ANALOG CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 5V; AVSS, BVSS, DVSS = 0V, VREFH = AVDD, VREFL = AVSS;
fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement Bandwidth = 20Hz~20kHz;
R
L
≥
600Ω; External circuit: Figure 12; unless otherwise specified)
Parameter
Resolution
Dynamic Characteristics
THD+N
(Note 5)
-100
-53
-97
-51
-97
-51
117
120
117
120
120
0.15
20
±2.4
-90
-
-87
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ppm/°C
Vpp
Ω
mA
fs=44.1kHz
0dBFS
BW=20kHz
-60dBFS
fs=96kHz
0dBFS
BW=40kHz
-60dBFS
fs=192kHz
0dBFS
BW=40kHz
-60dBFS
Dynamic Range (-60dBFS with A-weighted) (Note 6)
(Note 7)
S/N
(A-weighted)
(Note 8)
(Note 7)
Interchannel Isolation (1kHz)
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Output Voltage
Load Resistance
Output Current
Power Supplies
Power Supply Current
Normal Operation (PDN = “H”)
AVDD
DVDD(fs=44.1kHz)
DVDD(fs=96kHz)
DVDD(fs=192kHz)
AVDD + DVDD
60
7
10
17
-
-
-
-
110
mA
mA
mA
mA
mA
(Note 9)
(Note 10)
(Note 11)
0.3
-
±2.55
3.5
min
typ
max
24
Units
Bits
112
-
112
-
100
±2.25
600
Power-Down Mode (PDN = “L”)
AVDD + DVDD
(Note 12)
10
100
µA
Power Supply Rejection
(Note 13)
50
dB
Notes: 5. At 44.1kHz, measured by Audio Precision, System Two. Averaging mode.
At 96kHz and 192kHz, measured by ROHDE & SCHWARZ, UPD. Averaging mode.
Refer to the evaluation board manual.
6. 101dB at 16bit data and 116dB at 20bit data.
7. By Figure13. External LPF Circuit Example 2.
8. S/N does not depend on input bit length.
9. The voltage on (VREFH-VREFL) is held +5V externally.
10. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFH-VREFL).
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) =
±2.4Vpp×(VREFH-VREFL)/5.
11. For AC-load. 1kΩ for DC-load.
12. In the power-down mode. P/S = DVDD, and all other digital input pins including clock pins (MCLK, BICK and
LRCK) are held DVSS.
13. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held +5V.
MS0040-E-01
-5-
2001/4
京公网安备 11010802033920号
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