HM66AQB36104/HM66AQB18204
HM66AQB9404
36-Mbit QDR
TM
II SRAM
4-word Burst
REJ03C0048-0100
Rev.1.00
Aug.23.2006
Description
The HM66AQB36104 is a 1,048,576-word by 36-bit, the HM66AQB18204 is a 2,097,152-word by 18-bit, and the
HM66AQB9404 is a 4,194,304-word by 9-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and
K)
and are latched on the positive edge of K
and
K.
These products are suitable for applications which require synchronous operation, high speed, low voltage, high
density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
Features
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1.8 V
±
0.1 V power supply for core (V
DD
)
1.4 V to V
DD
power supply for I/O (V
DDQ
)
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR read and write operation
Four-tick burst for reduced address frequency
Two input clocks (K and
K)
for precise DDR timing at clock rising edges only
Two output clocks (C and
C)
for precise flight time and clock skew matching-clock and data delivered together to
receiving device
Internally self-timed write control
Clock-stop capability with
µs
restart
User programmable impedance output
Fast clock cycle time: 3.0 ns (333 MHz)/3.3 ns (300 MHz)/4.0 ns (250 MHz)/5.0 ns (200 MHz)/6.0 ns (167 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
Note: QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, IDT, NEC, Samsung, and Renesas Technology Corp.
Rev.1.00 Aug 23, 2006 page 1 of 20
HM66AQB36104/18204/9404
Pin Descriptions
Name
SA
I/O type
Input
Descriptions
Synchronous address inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. All transactions operate on a burst-of-four words (two clock periods of
bus activity). These inputs are ignored when device is deselected.
Synchronous read: When low, this input causes the address inputs to be registered and a READ
cycle to be initiated. This input must meet setup and hold times around the rising edge of K, and is
ignored on the subsequent rising edge of K.
Synchronous write: When low, this input causes the address inputs to be registered and a WRITE
cycle to be initiated. This input must meet setup and hold times around the rising edge of K, and is
ignored on the subsequent rising edge of K.
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals must meet setup and hold times around the rising
edges of K and
K
for each of the two rising edges comprising the WRITE cycle. See Byte Write
Truth Table for signal to data relationship.
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of
K. K
is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising
edges. These balls cannot remain V
REF
level.
Output clock: This clock pair provides a user-controlled means of tuning device output data. The
rising edge of
C
is used as the output timing reference for first and third output data. The rising
edge of C is used as the output timing reference for second and fourth output data. Ideally,
C
is
180 degrees out of phase with C. C and
C
may be tied high to force the use of K and
K
as the
output reference clocks instead of having to provide C and
C
clocks. If tied high, C and
C
must
remain high and not to be toggled during device operation. These balls cannot remain V
REF
level.
DLL disable: When low, this input causes the DLL to be bypassed for stable, low frequency
operation.
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. Q and CQ output impedance are set to 0.2
×
RQ, where RQ is a resistor from this
ball to ground. This ball can be connected directly to V
DDQ
, which enables the minimum impedance
mode. This ball cannot be connected directly to V
SS
or left unconnected.
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the JTAG
function is not used in the circuit.
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to V
SS
if the JTAG function is not
used in the circuit.
Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K
and
K
during WRITE operations. See Pin Arrangement figures for ball site location of individual
signals.
The
×9
device uses D0 to D8. Remaining signals are NC.
The
×18
device uses D0 to D17. Remaining signals are NC.
The
×36
device uses D0 to D35.
Synchronous echo clock outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals run freely and
do not stop when Q tri-states.
IEEE 1149.1 test output: 1.8 V I/O level.
Synchronous data outputs: Output data is synchronized to the respective C and
C,
or to the
respective K and
K
if C and
C
are tied high. This bus operates in response to
R
commands. See
Pin Arrangement figures for ball site location of individual signals.
The
×9
device uses Q0 to Q8. Remaining signals are NC.
The
×18
device uses Q0 to Q17. Remaining signals are NC.
The
×36
device uses Q0 to Q35.
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.
Power supply: Isolated output buffer supply. Nominally 1.5 V. 1.8 V is also permissible. See DC
Characteristics and Operating Conditions for range.
R
Input
W
Input
BW
BWn
Input
K,
K
Input
C,
C
Input
DOFF
ZQ
Input
Input
TMS
TDI
TCK
D0 to Dn
Input
Input
Input
CQ,
CQ
Output
TDO
Q0 to Qn
Output
Output
V
DD
V
DDQ
Supply
Supply
Rev.1.00 Aug 23, 2006 page 4 of 20
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