FAN2518S285X datasheet, PDF - EEWORLD Datasheet

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FAN2518S285X: DescriptionFixed Positive LDO Regulator, 2.85V, 0.075V Dropout, CMOS, PDSO5, SOT-23, 5 PIN; CategoryPower/power management The power supply circuit; File Size245KB，10 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/; Environmental Compliance

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FAN2518S285X Overview

Fixed Positive LDO Regulator, 2.85V, 0.075V Dropout, CMOS, PDSO5, SOT-23, 5 PIN

FAN2518S285X Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Fairchild
Parts packaging code	SOT-23
package instruction	LSSOP, TSOP5/6,.11,37
Contacts	5
Reach Compliance Code	unknown
ECCN code	EAR99
Adjustability	FIXED
Maximum drop-back voltage 1	0.075 V
Nominal dropback voltage 1	0.05 V
Maximum absolute input voltage	7 V
Maximum input voltage	6.5 V
Minimum input voltage	2.7 V
JESD-30 code	R-PDSO-G5
JESD-609 code	e3
length	2.9 mm
Maximum load regulation	0.057%
Number of functions	1
Output times	1
Number of terminals	5
Working temperatureTJ-Max	125 °C
Working temperature TJ-Min	-40 °C
Maximum output current 1	0.05 A
Maximum output voltage 1	2.907 V
Minimum output voltage 1	2.793 V
Nominal output voltage 1	2.85 V
Package body material	PLASTIC/EPOXY
encapsulated code	LSSOP
Encapsulate equivalent code	TSOP5/6,.11,37
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Regulator type	FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
Maximum seat height	1.45 mm
surface mount	YES
technology	CMOS
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.95 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Maximum voltage tolerance	2%
width	1.65 mm

FAN2518S285X Preview

www.fairchildsemi.com

FAN2518, FAN2519

50 mA CMOS LDO Regulators with Fast Start Enable

Features

•

Ultra Low Power Consumption

Enable optimized for CDMA time phases

50 mV dropout voltage at 50 mA

25 µA ground current at 50 mA

Enable/Shutdown Control

SOT23-5 package

Thermal limiting

300 mA peak current

wide variety of external capacitors, and the compact SOT23-5

surface-mount package. In addition, the FAN2518/19 family

offer the fast power-cycle time required in CDMA handset

applications. These products offer signiﬁcant improvements

over older BiCMOS designs and are pin-compatible with

many popular devices. The output is thermally protected

against overload.

The FAN2518 and FAN2519 devices are distinguished by

the assignment of pin 4:

FAN2518:

pin 4 – ADJ, allowing the user to adjust the

output voltage over a wide range using an external voltage

divider.

FAN2518-XX:

pin 4 – BYP, to which a bypass capacitor

may be connected for optimal noise performance. Output

voltage is ﬁxed, indicated by the sufﬁx XX.

FAN2519-XX:

pin 4 – ERR, a ﬂag which indicates that the

output voltage has dropped below the speciﬁed minimum

due to a fault condition.

The standard ﬁxed output voltages available are 2.5V, 2.6V,

2.7V, 2.8V, 2.85V, 3.0V, and 3.3V. Custom output voltage are

also available: please contact your local Fairchild Sales

Ofﬁce for information.

Applications

•

Cellular Phones and accessories

PDAs

Portable cameras and video recorders

Laptop, notebook and palmtop computers

Description

The FAN2518/19 family of micropower low-dropout voltage

regulators utilize CMOS technology to offer a new level of

cost-effective performance in GSM, TDMA, and CDMA

cellular handsets, Laptop and Notebook portable computers,

and other portable devices. Features include extremely low

power consumption and low shutdown current, low dropout

voltage, exceptional loop stability able to accommodate a

Block Diagrams

VIN

Bandgap

Error

Amplifier

VOUT

ADJ

Thermal

Sense

FAN2518

GND

FAN2518-XX

VIN

Bandgap

VOUT

ERR

Error

Amplifier

Thermal

Sense

VIN

Bandgap

VOUT

BYP

Error

Amplifier

GND

Thermal

Sense

FAN2519-XX

GND

REV. 1.0.6 2/14/03

PRODUCT SPECIFICATION

FAN2518/FAN2519

Pin Assignments

GND

OUT

ADJ/BYP/ERR

Pin No.

FAN2518

GND

ADJ

OUT

FAN2518-XX

GND

BYP

OUT

FAN2519-XX

GND

ERR

OUT

Pin Descriptions

Pin Name

ADJ

BYP

ERR

Pin No.

Type

Input

Passive

Open drain

Pin Function Description

FAN2518 Adjust.

Ratio of potential divider from VOUT to ADJ

determines output voltage.

FAN2518-XX Bypass.

Connect 470 pF capacitor for noise reduction.

FAN2519-XX Error.

Error flag output.

Output voltage < 95% of nominal.

Output voltage > 95% of nominal.

Enable.

Shutdown V

OUT

Enable V

OUT

Voltage Input.

Supply voltage input.

Voltage Output.

Regulated output voltage.

Ground.

Digital Input

OUT

GND

Power in

Power out

Power

Functional Description

Designed utilizing CMOS process technology, the

FAN2518/19 family of products are carefully optimized for

use in compact battery-powered devices, offering a unique

combination of low power consumption, extremely low

dropout voltages, high tolerance for a variety of output

capacitors, and the ability to disable the output to less than

1µA under user control. In the circuit, a difference ampliﬁer

controls the current through a series-pass P-Channel

MOSFET, comparing the load voltage at the output with an

onboard low-drift bandgap reference. The series resistance

of the pass P-Channel MOSFET is approximately 1

Ω

, result-

ing in an unusually low dropout voltage under load when

compared to older bipolar pass-transistor designs.

Protection circuitry is provided onboard for overload condi-

tions. In conditions where the device reaches temperatures

exceeding the speciﬁed maximums, an onboard circuit shuts

down the output, where it remains suspended until it has

cooled before re-enabling. The user is also free to shut down

the device using the Enable control pin at any time.

Careful design of the output regulator ampliﬁer assures loop

stability over a wide range of ESR values in the external

output capacitor. A wide range of values and types can be

accommodated, allowing the user to select a capacitor

meeting his space, cost, and performance requirements,

and enjoy reliable operation over temperature, load, and

tolerance variations.

REV. 1.0.6 2/14/03

FAN2518/FAN2519

PRODUCT SPECIFICATION

An Enable pin, available on all devices, allows the user to

shut down the regulator output to conserve power, reducing

supply current to less than 1µA. The output can then be

re-Enabled within 500µSec, fulﬁlling the fast power-cycling

needs of CDMA applications. Depending on the model

selected, other control and status functions are available at

pin 4 to enhance the operation of the device. The adjustable-

voltage versions utilize pin 4 to connect to an external

voltage divider which feeds back to the regulator error

ampliﬁer, thereby setting the voltage as desired. Two other

functions are available in the ﬁxed-voltage versions: in

noise-sensitive applications, an external Bypass capacitor

connection is provided that allows the user to achieve opti-

mal noise performance at the output, while the Error output

functions as a diagnostic ﬂag to indicate that the output

voltage has dropped more than 5% below the nominal ﬁxed

voltage.

more. Tantalum or aluminum electrolytic, or multilayer

ceramic types can all be used. A nominal value of at least

1µF is recommended.

Bypass Capacitor (FAN2518 Only)

In the ﬁxed-voltage conﬁguration, connecting a capacitor

between the bypass pin and ground can signiﬁcantly reduce

noise on the output. Values ranging from 470pF to 10nF can

be used, depending on the sensitivity to output noise in the

application.

At the high-impedance Bypass pin, care must be taken in the

circuit layout to minimize noise pickup, and capacitors must

be selected to minimize current loading (leakage). Noise

pickup from external sources can be considerable. Leakage

currents into the Bypass pin will directly affect regulator

accuracy and should be kept as low as possible; thus, high-

quality ceramic and ﬁlm types are recommended for their

low leakage characteristics. Cost-sensitive applications not

concerned with noise can omit this capacitor.

Applications Information

External Capacitors – Selection

The FAN2518/19 allows the user to utilize a wide variety of

capacitors compared to other LDO products. An innovative

design approach offers signiﬁcantly reduced sensitivity to

ESR (Effective Series Resistance), which degrades regulator

loop stability in older designs. While the improvements fea-

tured in the FAN2518/19 family greatly simplify the design

task, capacitor quality still must be considered if the designer

is to achieve optimal circuit performance. In general,

ceramic capacitors offer superior ESR performance, at a

lower cost and a smaller case size than tantalums. Those with

X7R or Y5Vdielectric offer the best temperature coefﬁcient

characteristics. The combination of tolerance and variation

over temperature in some capacitor types can result in signif-

icant variations, resulting in unstable performance over rated

conditions.

Control Functions

Enable Pin

Applying a voltage of 0.4V or less at the Enable pin will dis-

able the output, reducing the quiescent output current to less

than 1µA, while a voltage of 2.0V or greater will enable the

device. If this shutdown function is not needed, the pin can

simply be connected to the V

pin. Allowing this pin to ﬂoat

will cause erratic operation.

Error Flag (FAN2519 Only)

To indicate conditions such as input voltage dropout

(low V

), overheating, or overloading (excessive output

current), the ERR pin indicates a fault condition. It is an

open-drain output which is HIGH when the voltage at V

OUT

is greater than 95% of the nominal rated output voltage and

LOW when V

OUT

is less than 95% or the rated output volt-

age, as speciﬁed in the error trip level characteristics.

A logic pullup resistor of 100K

Ω

is recommended at this

output. The pin can be left disconnected if unused.

Thermal Protection

The FAN2518/19 is designed to supply high peak output

currents of up to 1A for brief periods, however this output

load will cause the device temperature to increase and

exceed maximum ratings due to power dissipation. During

output overload conditions, when the die temperature

exceeds the shutdown limit temperature of 150°C, onboard

thermal protection will disable the output until the tempera-

ture drops below this limit, at which point the output is

then re-enabled. During a thermal shutdown situation the

user may assert the power-down function at the Enable

pin, reducing power consumption to the minimum level

GND

· V

Input Capacitor

An input capacitor of 2.2µF (nominal value) or greater,

connected between the Input pin and Ground, located in

close proximity to the device, will improve transient

response and noise rejection. Higher values will offer supe-

rior input ripple rejection and transient response. An input

capacitor is recommended when the input source, either a

battery or a regulated AC voltage, is located far from the

device. Any good quality ceramic, tantalum, or metal ﬁlm

capacitor will give acceptable performance, however tanta-

lum capacitors with a surge current rating appropriate to the

application must be selected to avoid catastrophic failure.

Output Capacitor

An output capacitor is required to maintain regulator loop

stability. Unlike many other LDO regulators, the FAN2518/19

family of products are nearly insensitive to output capacitor

ESR. Stable operation will be achieved with a wide variety

of capacitors with ESR values ranging from 10m

Ω

to 10

Ω

REV. 1.0.6 2/14/03

PRODUCT SPECIFICATION

FAN2518/FAN2519

Thermal Characteristics

The FAN2518/19 is designed to supply 50mA at the speci-

ﬁed output voltage with an operating die (junction) tempera-

ture of up to 125°C. Once the power dissipation and thermal

resistance is known, the maximum junction temperature of

the device can be calculated. While the power dissipation is

calculated from known electrical parameters, the thermal

resistance is a result of the thermal characteristics of the

compact SOT23-5 surface-mount package and the surround-

ing PC Board copper to which it is mounted.

The power dissipation is equal to the product of the input-to-

output voltage differential and the output current plus the

ground current multiplied by the input voltage, or:

(

– V

OUT

+ V

GND

device to enter a thermal cycling loop, in which the circuit

enters a shutdown condition, cools, re-enables, and then

again overheats and shuts down repeatedly due to an

unmanaged fault condition.

Operation of Adjustable Version

The adjustable version of the FAN2518/19 includes an input

pin ADJ which allows the user to select an output voltage

ranging from 1.8V to near V

, using an external resistor

divider. The voltage V

ADJ

presented to the ADJ pin is fed to

the onboard error ampliﬁer which adjusts the output voltage

until V

ADJ

is equal to the onboard bandgap reference voltage

of 1.32V(typ). The equation is:

upper

OUT

= 1.32V

1 + ---------------

lower

The ground pin current I

GND

can be found in the charts

provided in the Electrical Characteristics section.

The relationship describing the thermal behavior of the

package is:



(

max

)

– T



(

max

)



-------------------------------





The total value of the resistor chain should not exceed

250K

Ω

total to keep the error ampliﬁer biased during

no-load conditions. Programming output voltages very near

need to allow for the magnitude and variation of the

dropout voltage V

over load, supply, and temperature

variations. Note that the low-leakage FET input to the

CMOS Error Ampliﬁer induces no bias current error to the

calculation.

where T

J(max)

is the maximum allowable junction tempera-

ture of the die, which is 125°C, and T

is the ambient operat-

ing temperature.

is dependent on the surrounding PC

board layout and can be empirically obtained. While the

(junction-to-case) of the SOT23-5 package is speciﬁed at

130°C /W, the

of the minimum PWB footprint will be at

least 235°C /W. This can be improved upon by providing a

heat sink of surrounding copper ground on the PWB.

Depending on the size of the copper area, the resulting

can range from approximately 180°C /W for one square inch

to nearly 130°C /W for 4 square inches. The addition of

backside copper with through-holes, stiffeners, and other

enhancements can also aid in reducing this value. The heat

contributed by the dissipation of other devices located

nearby must be included in design considerations.

Once the limiting parameters in these two relationships have

been determined, the design can be modiﬁed to ensure that

the device remains within speciﬁed operating conditions. If

overload conditions are not considered, it is possible for the

General PWB Layout Considerations

To achieve the full performance of the device, careful circuit

layout and grounding technique must be observed. Establish-

ing a small local ground, to which the GND pin, the output

and bypass capacitors are connected, is recommended, while

the input capacitor should be grounded to the main ground

plane. The quiet local ground is then routed back to the main

ground plane using feedthrough vias. In general, the high-

frequency compensation components (input, bypass, and

output capacitors) should be located as close to the device as

possible. The proximity of the output capacitor is especially

important to achieve optimal noise compensation from the

onboard error ampliﬁer, especially during high load condi-

tions. A large copper area in the local ground will provide the

heat sinking discussed above when high power dissipation

signiﬁcantly increases the temperature of the device.

Component-side copper provides signiﬁcantly better thermal

performance for this surface-mount device, compared to that

obtained when using only copper planes on the underside.

REV. 1.0.6 2/14/03

FAN2518/FAN2519

PRODUCT SPECIFICATION

Absolute Maximum Ratings

(beyond which the device may be damaged)

Parameter

Power Supply Voltages

(Measured to GND)

Enable Input (EN)

Applied voltage (Measured to GND)

ERR Output

Applied voltage (Measured to GND)

Power

Dissipation

Temperature

Junction

Lead Soldering (5 seconds)

Storage

Electrostatic Discharge

-65

150

260

150

°C

Internally limited

Min

Typ

Max

Unit

Notes:

1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only

if Operating Conditions are not exceeded.

2. Applied voltage must be current limited to specified range.

3. Based upon thermally limited junction temperature:

(

max

)

– T

= -------------------------------

4. Human Body Model is 4kV minimum using Mil Std. 883E, method 3015.7. Machine Model is 400V minimum using JEDEC

method A115-A.

Recommended Operating Conditions

Parameter

OUT

ERR

Input Voltage Range

Output Voltage Range, Adjustable

Enable Input Voltage

ERR Flag Voltage

Junction Temperature

Thermal resistance

-40

220

130

Min

2.7

REF

Nom

Max

6.5

-V

+125

Units

°C

°C/W

REV. 1.0.6 2/14/03

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FAN2518S285X Related Products

	FAN2518S285X	FAN2519S25X
Description	Fixed Positive LDO Regulator, 2.85V, 0.075V Dropout, CMOS, PDSO5, SOT-23, 5 PIN	Fixed Positive LDO Regulator, 2.5V, 0.075V Dropout, CMOS, PDSO5, SOT-23, 5 PIN
Is it Rohs certified?	conform to	conform to
Maker	Fairchild	Fairchild
Parts packaging code	SOT-23	SOT-23
package instruction	LSSOP, TSOP5/6,.11,37	LSSOP, TSOP5/6,.11,37
Contacts	5	5
Reach Compliance Code	unknown	unknow
ECCN code	EAR99	EAR99
Adjustability	FIXED	FIXED
Maximum drop-back voltage 1	0.075 V	0.075 V
Nominal dropback voltage 1	0.05 V	0.05 V
Maximum absolute input voltage	7 V	7 V
Maximum input voltage	6.5 V	6.5 V
Minimum input voltage	2.7 V	2.7 V
JESD-30 code	R-PDSO-G5	R-PDSO-G5
JESD-609 code	e3	e3
length	2.9 mm	2.9 mm
Maximum load regulation	0.057%	0.05%
Number of functions	1	1
Output times	1	1
Number of terminals	5	5
Working temperatureTJ-Max	125 °C	125 °C
Maximum output current 1	0.05 A	0.05 A
Maximum output voltage 1	2.907 V	2.55 V
Minimum output voltage 1	2.793 V	2.45 V
Nominal output voltage 1	2.85 V	2.5 V
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LSSOP	LSSOP
Encapsulate equivalent code	TSOP5/6,.11,37	TSOP5/6,.11,37
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified
Regulator type	FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR	FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
Maximum seat height	1.45 mm	1.45 mm
surface mount	YES	YES
technology	CMOS	CMOS
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.95 mm	0.95 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
Maximum voltage tolerance	2%	2%
width	1.65 mm	1.65 mm

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