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Cologne
Chip
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Copyright 1994-2001 Cologne Chip AG
All Rights Reserved
The information presented can not be considered as assured characteristics. Data can change without notice. Parts of the
information presented may be protected by patent or other rights. Cologne Chip products are not designed, intended, or
authorized for use in any application intended to support or sustain life, or for any other application in which the failure of
the Cologne Chip product could create a situation where personal injury or death may occur.
863 C
Revision History
Date
Jan. 2001
Feb. 2000
Nov. 1999
Aug. 1999
Cologne
Chip
Mar. 1999
Feb. 1999
Aug. 1998
May 1998
Remarks
Information added to section: GCI/IOM2 timing.
Information added to section: DMA access in processor mode, GCI frame structure.
Information added to section: Power down considerations.
Section added: Configuring test loops.
Information added to section: Processor interface modes, processor mode, FIFO
channel operation: receive channels, STATES register bit description, ISA-PC bus
or processor access timing, S/T interface activation/deactivation layer 1 for finite
state matrix for NT.
Changes made on: S/T modules part numbers and manufacturers.
Changes made on: CLKDEL register bit description.
Changes made on: DMA access in processor mode, Register bit description of
GCI/IOM2 bus section: Auxiliary channel handling, B_MODE register bit
description.
Changes made on: RESET characteristics, FIFO change must no longer be made
twice, watchdog/timer, automatically D-channel frame repetition, transparent mode,
power down considerations, TRxR register bit description, TRM register bit
description, SRAM access, S/T module part numbers and manufacturers, sample
circuitry.
Cologne
Chip
Cologne Chip AG
Eintrachtstrasse 113
D-50668 Köln
Germany
Tel.: +49 (0) 221 / 912 96 04
Fax: +49 (0) 221 / 912 96 05
http://www.CologneChip.com
http://www.CologneChip.de
info@CologneChip.com
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863 C
Contents
Cologne
Chip
1
General description............................................................................................................................ 6
1.1
Applications ..................................................................................................................................... 7
1.2
Mode description ............................................................................................................................. 8
1.2.1
ISA-PC mode .......................................................................................................................... 8
1.2.2
Processor interface modes....................................................................................................... 8
2
Pin description.................................................................................................................................... 9
2.1
ISA-PC bus and microprocessor interface....................................................................................... 9
2.2
S/T interface transmit signals ........................................................................................................ 11
2.3
S/T interface receive signals.......................................................................................................... 11
2.4
SRAM Interface ............................................................................................................................. 12
2.5
Oscillator........................................................................................................................................ 12
2.6
GCI/IOM2 bus interface ................................................................................................................ 13
2.7
GCI/IOM2 Timeslot enable signals ............................................................................................... 13
2.8
Interrupt outputs............................................................................................................................. 14
2.9
Miscellaneous pins......................................................................................................................... 14
2.10
Power supply ............................................................................................................................. 15
2.11
RESET characteristics............................................................................................................... 15
3
Functional description ..................................................................................................................... 16
3.1
ISA-PC mode ................................................................................................................................. 16
3.2
ISA-PC bus interface ..................................................................................................................... 18
3.3
Processor mode .............................................................................................................................. 19
3.3.1
DMA access in processor mode............................................................................................ 20
3.4
Internal HFC-S+ register description............................................................................................. 21
3.4.1
FIFO control registers ........................................................................................................... 21
3.4.1.1
FIFO select register........................................................................................................... 21
3.4.1.2
FIFO registers ................................................................................................................... 21
3.4.2
Registers of the S/T section .................................................................................................. 23
3.4.3
Registers of the GCI/IOM2 bus section ................................................................................ 24
3.4.4
Interrupt and status registers ................................................................................................. 25
3.5
Timer.............................................................................................................................................. 26
3.6
Watchdog ....................................................................................................................................... 26
3.7
FIFOs ............................................................................................................................................. 27
3.7.1
FIFO channel operation......................................................................................................... 28
3.7.1.1
Send channels (B1, B2 and D transmit)............................................................................ 29
3.7.1.2
Automatically D-channel frame repetition ....................................................................... 29
3.7.1.3
FIFO full condition in send channels................................................................................ 29
3.7.1.4
Receive Channels (B1, B2 and D receive) ....................................................................... 30
3.7.1.5
FIFO full condition in receive channels ........................................................................... 31
3.7.1.6
FIFO reset ......................................................................................................................... 32
3.7.2
Transparent mode of HFC-S+............................................................................................... 32
3.8
External SRAM.............................................................................................................................. 33
3.9
Power down considerations ........................................................................................................... 33
3.10
Configuring test loops ............................................................................................................... 34
4
Register bit description.................................................................................................................... 35
4.1
Register bit description of the FIFO select register ....................................................................... 35
4.2
Register bit description of S/T section .......................................................................................... 35
4.3
Register bit description of GCI/IOM2 bus section ........................................................................ 39
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863 C
4.4
4.5
5
Cologne
Chip
Register bit description of CONNECT register............................................................................. 42
Register bit description of interrupt, status and control registers.................................................. 43
Electrical characteristics ................................................................................................................. 48
6
Timing characteristics ..................................................................................................................... 51
6.1
ISA-PC bus or processor access .................................................................................................... 51
6.2
SRAM access................................................................................................................................. 52
6.3
GCI/IOM2 bus clock and data alignment for Mitel ST
TM
bus....................................................... 53
6.4
GCI/IOM2 timing .......................................................................................................................... 54
6.4.1
Master mode.......................................................................................................................... 54
6.4.2
Slave mode ............................................................................................................................ 55
7
S/T interface circuitry...................................................................................................................... 56
7.1
External receiver circuitry ............................................................................................................. 56
7.2
External transmitter circuitry......................................................................................................... 57
7.3
Oscillator circuitry ......................................................................................................................... 60
8
State matrices for NT and TE ......................................................................................................... 61
8.1
S/T interface activation/deactivation layer 1 for finite state matrix for NT .................................. 61
8.2
Activation/deactivation layer 1 for finite state matrix for TE ....................................................... 62
9
Binary organisation of the frames .................................................................................................. 63
9.1
S/T frame structure ........................................................................................................................ 63
9.2
GCI frame structure ....................................................................................................................... 64
10 Clock synchronisation...................................................................................................................... 65
10.1
Clock synchronisation in NT-mode........................................................................................... 65
10.2
Clock synchronisation in TE-mode ........................................................................................... 66
11
12
HFC-S+ package dimensions .......................................................................................................... 67
ISDN PC card sample circuitry with HFC-S+ .............................................................................. 68
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863 C
Figures
Cologne
Chip
Figure 1: HFC-S+ block diagram.................................................................................................................. 7
Figure 2: Pin Connection .............................................................................................................................. 9
Figure 3: FIFO Organisation (shown for B-channel, similar for D-channel) ............................................. 28
Figure 4: FIFO Data Organisation .............................................................................................................. 30
Figure 5: Function of the CONNECT register bits..................................................................................... 42
Figure 6: GCI/IOM2 bus clock and data alignment.................................................................................... 53
Figure 7: External receiver circuitry........................................................................................................... 56
Figure 8: External transmitter circuitry ...................................................................................................... 57
Figure 9: Oscillator Circuitry...................................................................................................................... 60
Figure 10: Frame structure at reference point S and T ............................................................................... 63
Figure 11: Single channel GCI format........................................................................................................ 64
Figure 12: Clock synchronisation in NT-mode .......................................................................................... 65
Figure 13: Clock synchronisation in TE-mode ........................................................................................... 66
Figure 14: HFC-S+ package dimensions .................................................................................................... 67
Tables
Table 1: Mode selection................................................................................................................................ 8
Table 2: Selected I/O address after reset .................................................................................................... 16
Table 3: DMA access in processor mode ................................................................................................... 20
Table 4: SRAM and FIFO size ................................................................................................................... 33
Table 5: S/T module part numbers and manufacturer ................................................................................ 59
Table 6: Activation/deactivation layer 1 for finite state matrix for NT ..................................................... 61
Table 7: Activation/deactivation layer 1 for finite state matrix for TE...................................................... 62
Timing Diagrams
Timing diagram 1: ISA-PC bus or microprocessor access ......................................................................... 51
Timing diagram 2: SRAM access ............................................................................................................... 52
Timing diagram 3: GCI/IOM2 timing......................................................................................................... 54
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