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PDM41024LA20TSO

Description
Standard SRAM, 128KX8, 20ns, CMOS, PDSO32
Categorystorage    storage   
File Size79KB,8 Pages
ManufacturerParadigm Technology Inc
Download Datasheet Parametric View All

PDM41024LA20TSO Overview

Standard SRAM, 128KX8, 20ns, CMOS, PDSO32

PDM41024LA20TSO Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerParadigm Technology Inc
package instructionSOJ, SOJ32,.34
Reach Compliance Codeunknown
ECCN code3A991.B.2.B
Maximum access time20 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-J32
JESD-609 codee0
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of ports1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX8
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ32,.34
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum standby current0.0005 A
Minimum standby current2 V
Maximum slew rate0.14 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
PDM41024
1 Megabit Static RAM
128K x 8-Bit
Features
s
High-speed access times
Com’l: 10, 12, 15, 17 and 20 ns
Ind’l: 12, 15, 17 and 20 ns
s
Low power operation (typical)
- PDM41024SA
Active: 400 mW
Standby: 150 mW
- PDM41024LA
Active: 350 mW
Standby: 100 mW
s
Single +5V (±10%) power supply
s
TTL-compatible inputs and outputs
s
Packages
Plastic SOJ (300 mil) - TSO
Plastic SOJ (400 mil) - SO
Plastic TSOP - T
1
2
3
4
5
6
7
8
9
10
11
12
Description
The PDM41024 is a high-performance CMOS static
RAM organized as 131,072 x 8 bits. This product is
produced in Paradigm’s proprietary CMOS
technology which offers the designer the highest
speed parts. Writing is accomplished when the write
enable (WE) and the chip enable (CE1) inputs are
both LOW and CE2 is HIGH. Reading is
accomplished when WE and CE2 remain HIGH and
CE1 and OE are both LOW.
The PDM41024 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41024 comes in two versions,
the standard power version PDM41024SA and a low
power version the PDM41024LA. The two versions
are functionally the same and only differ in their
power consumption.
The PDM41024 is available in a 32-pin plastic TSOP,
300-mil and 400-mil plastic SOJ.
Functional Block Diagram
Rev. 2.1 - 7/17/96
4-25
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