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IDT70V9169L6BFG

Description
Dual-Port SRAM, 16KX9, 15ns, CMOS, PBGA100, 10 X 10MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-100
Categorystorage    storage   
File Size187KB,16 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

IDT70V9169L6BFG Overview

Dual-Port SRAM, 16KX9, 15ns, CMOS, PBGA100, 10 X 10MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-100

IDT70V9169L6BFG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeBGA
package instruction10 X 10MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-100
Contacts100
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time15 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 codeS-PBGA-B100
JESD-609 codee3
length10 mm
memory density147456 bit
Memory IC TypeDUAL-PORT SRAM
memory width9
Number of functions1
Number of terminals100
word count16384 words
character code16000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16KX9
Package body materialPLASTIC/EPOXY
encapsulated codeLFBGA
Package shapeSQUARE
Package formGRID ARRAY, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.5 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width10 mm
HIGH-SPEED 3.3V 16/8K X 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features:
IDT70V9169/59L
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9ns (max.)
– Industrial: 7.5ns (max.)
Low-power operation
– IDT70V916/59L/59L
Active: 450mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE
pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for 83 MHz
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin fine pitch Ball Grid Array (fpBGA) packages.
Functional Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
R/W
R
OE
R
CE
0R
CE
1R
1
0
0/1
1
0
0/1
FT/PIPE
L
0/1
1
0
0
1
0/1
FT/PIPE
R
I/O
0L
- I/O
8L
I/O
0R
- I/O
8R
I/O
Control
I/O
Control
A
13L
(1)
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
NOTE:
1. A
13
is a NC for IDT70V9159.
A
13R
(1)
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
5655 drw 01
AUGUST 2003
1
©2003 Integrated Device Technology, Inc.
DSC-5655/2
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