IDT74LVCH2574A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS OCTAL EDGE-
TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS, 5 VOLT
TOLERANT I/O AND BUS-HOLD
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 1.27mm pitch SOIC, 0.65mm pitch SSOP,
0.635mm pitch QSOP, 0.65mm pitch TSSOP packages
– Extended commercial range of – 40°C to +85°C
– V
CC
= 3.3V ±0.3V, Normal Range
– V
CC
= 2.3V to 3.6V, Extended Range
– CMOS power levels (0.4µW typ. static)
– Rail-to-Rail output swing for increased noise margin
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
Drive Features for LVCH2574A:
– Balanced Output Drivers:
±12mA
– Low switching noise
–
–
IDT74LVCH2574A
N
O
FO T
R
R E
N CO
EW M
M
D E
ES N
D
IG E
N D
S
APPLICATIONS:
DESCRIPTION:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
The LVCH2574A octal edge-triggered D-type flip-flop is built using
advanced dual-metal CMOS technology. The device features 3-state
outputs designed specifically for driving highly capacitive or relatively low-
impedance loads. The LVCH2574A is particularly suitable for implementing
buffer registers, input-output (I/O) ports, bidirectional bus drivers, and
working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set
to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs
in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly.
OE
does not affect the internal operations of the flip-flops.
Old data can be retained or new data can be entered while the outputs are
in the high-impedance state.
The LVCH2574A has series resistors in the device output structure which
will significantly reduce line noise when used with light loads. This driver has
been developed to drive
±
12mA at the designated thresholds.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
The LVCH2574A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
OE
1
CLK
11
C
1
1
D
2
19
1
D
1
Q
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-4941/-
IDT74LVCH2574A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
ABSOLUTE MAXIMUM RATINGS
V
CC
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
8
Q
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through
each V
CC
or GND
(1)
Unit
V
°C
mA
mA
mA
8LVC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
SO20-2
SO20-7
16
SO20-8
SO20-9
15
Max.
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
±100
14
13
12
11
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
GND
CLK
CAPACITANCE
(T
A
= +25°C, f = 1.0MH
Z
)
Symbol
C
IN
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
5.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
8LVC Link
SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
C
OUT
C
I/O
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
OE
CLK
xD
xQ
Description
Output-enable Input (Active LOW)
Clock Input
Data Inputs
(1)
3-State Outputs
OE
L
L
L
H
FUNCTION TABLE
(each flip-flop)
Inputs
CLK
↑
↑
H or L
X
xD
H
L
X
X
(1)
Outputs
xQ
H
L
Q
0
Z
NOTE:
1. These pins have “Bus-hold”. All other pins are standard inputs,
outputs, or I/Os.
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑
= LOW-to-HIGH Transition
Q
0
= Level of Q before the indicated steady-state conditions were
established.
2
IDT74LVCH2574A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= – 40°C To +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
(3)
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
3.6
≤
V
IN
≤
5.5V
(2)
Quiescent Power Supply
Current Variation
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
Vcc = 3.0 – 3.6V
—
—
—
—
—
—
—
– 0.7
100
—
—
—
±50
– 1.2
—
10
10
500
µA
8LVC Link
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
V
O
= 0 to 5.5V
Min.
1.7
2
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
±10
Unit
V
V
µA
µA
µA
V
mV
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. This applies in the disabled state only.
3. Per control input. Excludes Bus-Hold current.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
—
—
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
3
IDT74LVCH2574A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 4mA
I
OH
= – 6mA
V
CC
= 2.7V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
I
OH
= – 4mA
I
OH
= – 8mA
I
OH
= – 6mA
I
OH
= – 12mA
I
OL
= 0.1mA
I
OL
= 4mA
I
OL
= 6mA
I
OL
= 4mA
I
OL
= 8mA
I
OL
= 6mA
I
OL
= 12mA
Min.
V
CC
– 0.2
1.9
1.7
2.2
2
2.4
2
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
8LVC Link
Unit
V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to +85°C.
SWITCHING CHARACTERISTICS
Symbol
t
PHL
t
PLH
t
PZH
t
PZL
t
PHZ
t
PLZ
t
W
t
SU
t
H
t
SK(0)
Parameter
Propagation Delay
CLK to xQ
Output Enable Time
OE
to xQ
Output Disable Time
OE
to xQ
Pulse Duration, CLK HIGH or LOW
Setup Time, data before CLK↑
Hold Time, data after CLK↑
Output Skew
(2)
Min.
(1)
V
CC
= 2.7V
Min.
1.5
1.5
1.5
3.3
2.5
1.5
—
Max.
9.5
9.5
7
—
—
—
—
V
CC
= 3.3V±0.3V
Min.
1.5
1.5
1.5
3.3
2.5
1.5
—
Max.
8.5
8.5
6.5
—
—
—
500
Unit
ns
ns
ns
ns
ns
ns
ps
V
CC
= 2.5V±0.2V
Max.
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVCH2574A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V ±0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
V
CC
(2)
= 2.5V ±0.2V Unit
2 x Vcc
V
Vcc
V
CC
/ 2
150
150
30
V
V
mV
mV
pF
8LVC Link
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
(1, 2)
Generator
V
IN
D.U.T.
500
Ω
C
L
V
OUT
V
LOAD
Open
GND
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SW ITCH
NORMALLY
V
LOAD
LOW
t
PZH
OUTPUT
SWITCH
NORMALLY
GND
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
OL+
V
LZ
V
OL
V
OH
V
OH-
V
HZ
0V
LVC Link
R
T
LVC Link
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
t
REM
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
LVC Link
GND
Open
8LVC Link
OUTPUT SKEW - tsk (x)
INPUT
t
PLH1
t
PHL1
SYNCHRONOUS
CONTROL
t
SU
t
H
V
IH
V
T
0V
V
OH
PULSE WIDTH
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
LVC Link
OUTPUT 1
t
SK
(x)
t
SK
(x)
V
T
V
OL
V
OH
V
T
OUTPUT 2
t
PLH2
t
PHL2
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
LVC
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
Link
5
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