IDT74ALVC16820
3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 10-BIT
FLIP-FLOP WITH DUAL
3-STATE OUTPUTS
FEATURES:
DESCRIPTION:
IDT74ALVC16820
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
R
FO E
C N
R O
O
N M T
EW M
EN
D
ES DE
IG D
N
S
1
OE
1
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
This 10-bit flip-flop is built using advanced dual metal CMOS technology.
The flip-flops of the ALVC16820 are edge-triggered D-type flip-flops. On the
positive transition of the clock (CLK) input, the device provides true data at
the Q outputs.
A buffered output-enable (OE) input can be used to place the ten outputs
in either a normal logic state (high or low logic level) or a high-impedance
state. In the high impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without the need for interface or pullup
components.
OE
input does not affect the internal operation of the flip-flops.
Old data can be retained or new data can be entered while the outputs are
in the high-impedance state.
The ALVC16820 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
2
OE
28
CLK
56
2
1
Q
1
C
1
3
D
1
55
1
Q
2
D
1
TO 9 OTHER CHANNELS
AUGUST 1999
DSC-4541/2
IDT74ALVC16820
3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
V
TERM
(2)
Terminal Voltage with Respect to GND
V
TERM
(3)
Terminal Voltage with Respect to GND
–0.5 to +4.6
–0.5 to V
CC
+0.5
–65 to +150
–50 to +50
±50
–50
±100
Unit
V
V
°C
mA
mA
mA
mA
1
OE
1
Q
1
1
Q
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLK
D
1
NC
GND
D
2
NC
V
CC
D
3
NC
D
4
GND
NC
D
5
NC
D
6
NC
D
7
GND
NC
D
8
NC
V
CC
D
9
NC
GND
D
10
NC
NC
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
GND
2
Q
1
2
Q
2
V
CC
3
Q
1
3
Q
2
4
Q
1
GND
4
Q
2
5
Q
1
5
Q
2
6
Q
1
6
Q
2
7
Q
1
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
GND
7
Q
2
8
Q
1
8
Q
2
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
Dx
CLK
xQx
xOE
Data Inputs
Clock Input
3-State Outputs
3-State Output Enable Inputs (Active LOW)
Description
V
CC
9
Q
1
9
Q
2
GND
10
Q
1
10
Q
2
2
OE
FUNCTION TABLE
(EACH FLIP-FLOP)
(1)
Inputs
Outputs
Dx
H
L
X
X
xQx
H
L
Q
(2)
0
SSOP/ TSSOP/ TVSOP
TOP VIEW
xOE
L
L
L
H
CLK
↑
↑
L
X
Z
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑
= LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
2
IDT74ALVC16820
3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
–0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
±10
±10
–1.2
—
40
V
mV
µA
µA
µA
µA
V
Unit
V
Quiescent Power Supply Current
Variation
—
—
750
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
3
IDT74ALVC16820
3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Outputs enabled
Power Dissipation Capacitance per Flip-Flop
Outputs enabled
38
46
Parameter
Power Dissipation Capacitance per Flip-Flop
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
60
V
CC
= 3.3V ± 0.3V
Typical
63
pF
Unit
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
W
t
SU
t
H
t
SK(O)
Parameter
Propagation Delay
CLK to xQx
Output Enable Time
OEx
to xQx
Output Disable Time
OEx
to xQx
Pulse Width, CLK HIGH or LOW
Set-up Time HIGH or LOW
data before CLK↑
Hold Time HIGH or LOW
data before CLK↑
Output Skew
(2)
—
—
—
—
—
—
—
500
ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
V
CC
= 2.7V
Min.
—
—
—
3.3
1.8
1.1
Max.
5.5
6.1
5
—
—
—
V
CC
= 3.3V ± 0.3V
Min.
—
—
—
3.3
1.4
1
Max.
4.5
5.7
4.5
—
—
—
V
CC
= 3.3V ± 0.15V
Min.
1
1
1.3
3.3
1.4
1
Max.
4
5
4.5
—
—
—
Unit
ns
ns
ns
ns
ns
ns
Min.
1
1
1
3.3
1.7
1.1
Max.
5.9
6.4
5.7
—
—
—
4
IDT74ALVC16820
3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALV C Link
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 3.3V±0.3V V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
500
Ω
Pulse
Generator
(1, 2)
SAME PHASE
INPU T TRAN SITION
V
CC(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
V
LOAD
Open
GND
t
PLH
OU TPUT
t
PLH
OPPOSITE PHASE
INPU T TRAN SITION
t
PHL
6
2.7
1.5
300
300
50
t
PHL
Propagation Delay
ENABLE
CON TROL
IN PUT
t
PZL
DISABLE
V
IN
D .U .T.
V
OUT
V
IH
V
T
0V
V
LOAD/2
V
OL
+ V
LZ
V
OL
V
OH
V
OH -
V
HZ
0V
ALV C Link
t
PLZ
V
LOAD/2
V
T
t
PHZ
V
T
0V
R
T
500
Ω
C
L
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2ns; t
R
≤
2ns.
OUTPU T
SW ITCH
NOR MALLY
CLO SED
LOW
t
PZ H
OU TPUT
SW ITCH
NORMALLY
O PE N
H IGH
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALVC Link
Enable and Disable Times
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
V
IH
INPU T
V
T
0V
V
OH
OUTPUT 1
V
T
V
OL
V
OH
OUTPUT 2
t
PLH2
t
PHL2
ALVC Link
DATA
INPUT
TIMING
INPU T
ASYNC HRON OU S
CON TROL
SYNC HRON OU S
CON TROL
t
SU
t
H
t
R EM
t
SU
t
H
Set-up, Hold, and Release Times
t
PLH1
t
PHL1
LOW -H IGH -LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
V
T
t
SK
(x)
t
SK
(x)
V
T
ALVC Link
V
T
V
OL
Pulse Width
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PH L2
-
t
PHL1
Output Skew - t
SK
(
X
)
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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