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Datasheet> All Categories > logic> logic> IDT74FCT162H952CTPAG
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IDT74FCT162H952CTPAG

Description
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TSSOP-56
Categorylogic    logic   
File Size77KB，7 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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IDT74FCT162H952CTPAG Overview

Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TSSOP-56

IDT74FCT162H952CTPAG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP-56
Contacts56
Reach Compliance Codecompliant
Other featuresWITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
seriesFCT
JESD-30 codeR-PDSO-G56
JESD-609 codee3
length14 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeREGISTERED BUS TRANSCEIVER
Humidity sensitivity level1
Number of digits8
Number of functions2
Number of ports2
Number of terminals56
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE WITH SERIES RESISTOR
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)6.3 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width6.1 mm

IDT74FCT162H952CTPAG Preview

IDT74FCT162H952AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
16-BIT REGISTERED
TRANSCEIVER
FEATURES:
•
•
•
•
•
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK(o)
(Output Skew) < 250ps
Low input and output leakage
≤
1µA (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull up resistors
• Available in SSOP and TSSOP packages
IDT74FCT162H952AT/CT/ET
DESCRIPTION:
The FCT162H952T 16-bit registered transceiver is built using advanced
dual metal CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit D-type registered transceivers with
separate input and output control for independent control of data flow in either
direction. For example, the A-to-B Enable (xCEAB) must be low to enter data
from the A port. xCLKAB controls the clocking function. When xCLKAB toggles
from low-to-high, the data present on the A port will be clocked into the register.
xOEAB performs the output enable function on the B port. Data flow from the
B port to A port is similar but requires using xCEBA, xCLKBA, and xOEBA inputs.
Full 16-bit operation is achieved by tying the control pins of the independent
transceivers together.
The FCT162H952T has "Bus Hold" which retains the input's last state
whenever the input goes to high impedance. This prevents "floating" inputs and
eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
54
31
1
CE BA
55
2
CE BA
30
1
CLKBA
1
2
CLKBA
28
1
OE AB
3
2
OE AB
26
1
CE AB
2
2
CE AB
27
1
CLKAB
56
2
CLKAB
29
1
OE BA
5
2
OE BA
C
CE
D
15
52
1
A
1
2
A
1
1
B
1
C
CE
D
42
2
B
1
C
CE
D
C
CE
D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHE R CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2002 Integrated Device Technology, Inc.
NOVEMBER 2002
DSC-5441/3
IDT74FCT162H952AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OEAB
1
CLKAB
1
CEAB
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to 7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEBA
1
CLKBA
1
CEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
TERM(2)
Terminal Voltage with Respect to GND
V
TERM(3)
T
STG
I
OUT
GND
1
A
1
1
A
2
GND
1
B
1
1
B
2
V
CC
1
A
3
1
A
4
1
A
5
V
CC
1
B
3
1
B
4
1
B
5
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.V
CC
terminals.
3. Outputs and I/O terminals for FCT162XXX.
GND
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
2
A
3
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
GND
2
A
4
2
A
5
2
A
6
GND
2
B
4
2
B
5
2
B
6
NOTE:
1. This parameter is measured at characterization but not tested.
V
CC
2
A
7
2
A
8
V
CC
2
B
7
2
B
8
GND
2
CEAB
2
CLKAB
2
OEAB
GND
2
CEBA
2
CLKBA
2
OEBA
FUNCTION TABLE
(1, 3)
Inputs
xCEAB
xCLKAB
X
L
↑
↑
X
xOEAB
L
L
L
L
H
xAx
X
X
L
H
X
H
X
L
L
X
Outputs
xBx
B
(2)
B
(2)
L
H
Z
SSOP/ TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
xOEAB
xOEBA
xCEAB
xCEBA
xCLKAB
xCLKBA
xAx
xBx
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Clock Enable Input (Active LOW)
B-to-A Clock Enable Input (Active LOW)
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
(1)
B-to-A Data Inputs or A-to-B 3-State Outputs
(1)
NOTES:
1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA,
and xOEBA.
2. Level of B before the indicated steady-state input conditions were established.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
↑
= LOW-to-HIGH Transition
Z = High-impedance
NOTE:
1. These pins have “Bus Hold”. All other pins are standard inputs, outputs or I/Os.
2
IDT74FCT162H952AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
Parameter
Input HIGH Level
Input LOW Level
Input
HIGH
Current
(4)
I
IL
Input
LOW
Current
(4)
I
BHH
I
BHL
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Bus-hold Sustain
Current
(
4)
High Impedance Output Current
(3-State Output pins)
(
5, 6)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max
V
IN
= GND or V
CC
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
V
CC
= Max.
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Standard Input
(
5)
Min.
2
—
Typ.
(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–0.7
–140
100
5
Max.
—
0.8
±1
±1
±100
±100
±1
±1
±100
±100
—
—
±1
±1
–1.2
–250
—
500
Unit
V
V
µA
V
CC
= Max.
V
I
= V
CC
—
—
—
—
Standard I/O
(
5)
Bus-hold Input
Bus-hold I/O
Standard Input
(
5)
Standard I/O
(
5)
V
I
= GND
—
—
—
—
Bus-hold Input
Bus-hold I/O
Bus-hold Input
V
CC
= Min.
V
I
= 2V
V
I
= 0.8V
V
O
= 2.7V
V
O
= 0.5V
–50
50
—
—
—
–80
—
—
µA
µA
V
mA
mV
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
V
CC
= Min.
I
OH
= –24mA
V
IN
= V
IH
or V
IL
V
CC
= Min.
I
OL
= 24mA
V
IN
= V
IH
or V
IL
Min.
60
–60
2.4
—
Typ.
(2)
115
–115
3.3
0.3
Max.
200
–200
—
0.55
Unit
mA
mA
V
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Pins with Bus-hold are identified in the pin description.
5. The test limit for this parameter is ±5µA at T
A
= –55°C.
6. Does not include Bus-hold I/O pins.
3
IDT74FCT162H952AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
xOEAB or xOEBA = GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz (xCLKAB)
50% Duty Cycle
xOEAB = xCEAB = GND
xOEBA = V
CC
One Bit Toggling
f
i
= 5MHz
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz (xCLKAB)
50% Duty Cycle
xOEAB = xCEAB = GND
xOEBA = V
CC
Sixteen Bits Toggling
f
i
= 2.5MHz
50% Duty Cycle
Min.
—
V
IN
= V
CC
V
IN
= GND
—
Typ.
(2)
0.5
75
Max.
1.5
120
Unit
mA
µA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
0.8
1.7
mA
V
IN
= 3.4V
V
IN
= GND
—
1.3
3.2
V
IN
= V
CC
V
IN
= GND
—
3.8
6.5
(5)
V
IN
= 3.4V
V
IN
= GND
—
8.3
20
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
ΔI
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
ΔI
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
4
IDT74FCT162H952AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT162H952AT
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
t
H
t
W
t
SK(o)
Parameter
Propagation Delay
xCLKAB, xCLKBA to xBx, xAx
Output Enable Time
xOEBA, xOEAB to xAx, xBx
Output Disable Time
xOEBA, xOEAB to xAx, xBx
Set-up Time, HIGH or LOW
xAx, xBx to xCLKAB, xCLKBA
Hold Time HIGH or LOW
xAx, xBx to xCLKAB, xCLKBA
Set-up Time, HIGH or LOW
xCEAB, xCEBA to xCLKAB, xCLKBA
Hold Time HIGH or LOW
xCEAB, xCEBA to xCLKAB, xCLKBA
Pulse Width HIGH or LOW
xCLKAB or xCLKBA
(3)
Output Skew
(4)
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
Min.
(2)
2
1.5
1.5
2.5
2
3
2
3
—
Max.
10
10.5
10
—
—
—
—
—
0.5
FCT162H952CT
Min.
(2)
2
1.5
1.5
2.5
1.5
3
2
3
—
Max.
6.3
7
6.5
—
—
—
—
—
0.5
FCT162H952ET
Min.
(2)
1.5
1.5
1.5
1.5
0
2
0
3
—
Max.
3.7
4.4
3.6
—
—
—
—
—
0.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Guaranteed but not tested.
4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
5
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IDT74FCT162H952CTPAG Related Products

IDT74FCT162H952CTPAG IDT74FCT162H952ATPAG IDT74FCT162H952ETPVG IDT74FCT162H952ETPAG
Description Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TSSOP-56 Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TSSOP-56 Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, SSOP-56 Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TSSOP-56
Is it lead-free? Lead free Lead free Lead free Lead free
Is it Rohs certified? conform to conform to conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP SSOP TSSOP
package instruction TSSOP-56 TSSOP-56 SSOP-56 TSSOP-56
Contacts 56 56 56 56
Reach Compliance Code compliant compliant compliant compliant
Other features WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
series FCT FCT FCT FCT
JESD-30 code R-PDSO-G56 R-PDSO-G56 R-PDSO-G56 R-PDSO-G56
JESD-609 code e3 e3 e3 e3
length 14 mm 14 mm 18.415 mm 14 mm
Load capacitance (CL) 50 pF 50 pF 50 pF 50 pF
Logic integrated circuit type REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER
Humidity sensitivity level 1 1 1 1
Number of digits 8 8 8 8
Number of functions 2 2 2 2
Number of ports 2 2 2 2
Number of terminals 56 56 56 56
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C
Output characteristics 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR
Output polarity TRUE TRUE TRUE TRUE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP SSOP TSSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260 260 260
propagation delay (tpd) 6.3 ns 10 ns 3.7 ns 3.7 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm 2.794 mm 1.2 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V
surface mount YES YES YES YES
technology CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed MATTE TIN Matte Tin (Sn) - annealed
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.5 mm 0.5 mm 0.635 mm 0.5 mm
Terminal location DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 30 30 30
width 6.1 mm 6.1 mm 7.5 mm 6.1 mm

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