IDT74ALVCH16952
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT
REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
–
–
–
–
–
–
–
–
–
–
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
Extended commercial range of – 40°C to + 85°C
V
CC
= 3.3V ± 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V ± 0.2V
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
IDT74ALVCH16952
DESCRIPTION:
This 16-bit registered transceiver is built using advanced dual metal
CMOS technology. The ALVCH16952 contains two sets of D-type flip-flops
for temporary storage of data flowing in either direction. This device can
be used as two 8-bit transceivers or one 16-bit transceiver. Data on the
A or B bus is stored in the registers on the low-to-high transition of the clock
(CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or
CLKENBA)
input is low. Taking the output-enable (OEAB or
OEBA)
input
low accesses the data on either port.
The ALVCH16952 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH16952 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
Drive Features for ALVCH16952:
– High Output Drivers: ±24mA
– Suitable for heavy loads
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
Functional Block Diagram
1
CLKENBA
1
CLKBA
1
OEAB
54
2
CLKENBA
2
CLKBA
2
OEAB
31
55
1
30
28
1
CLKENAB
3
2
CLKENAB
26
1
CLKAB
2
2
CLKAB
27
1
OEBA
56
2
OEBA
29
C
1
A
1
5
C
52
2
A
1
1
B
1
15
CE
D
C
CE
D
CE
D
C
CE
D
42
2
B
1
TO SEVEN OTH ER CH ANNELS
TO SEVEN OTH ER CH ANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4227/-
IDT74ALVCH16952
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OEAB
1
CLKAB
1
CLKENAB
ABSOLUTE MAXIMUM RATING
56
55
54
53
52
51
50
49
48
47
46
45
1
OEBA
1
CLKBA
1
CLKENBA
(1)
Unit
V
V
°C
mA
mA
mA
mA
NEW16link
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
V
TERM(2)
V
TERM(3)
T
STG
GND
1
A
1
1
A
2
GND
1
B
1
1
B
2
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
Max.
– 0.5 to + 4.6
– 0.5 to
V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
I
OUT
I
IK
I
OK
I
CC
I
SS
V
CC
1
A
3
1
A
4
1
A
5
V
CC
1
B
3
1
B
4
1
B
5
GND
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
2
A
3
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
44
SO56-1
SO56-2 43
SO56-3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
PIN DESCRIPTION
Pin Names
xOEAB
xOEBA
xCLKENAB
xCLKENBA
xCLKAB
xCLKBA
xAx
xBx
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Clock Enable Input (Active LOW)
B-to-A Clock Enable Input (Active LOW)
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
(1)
B-to-A Data Inputs or A-to-B 3-State Outputs
(1)
GND
2
A
4
2
A
5
2
A
6
GND
2
B
4
2
B
5
2
B
6
V
CC
2
A
7
2
A
8
V
CC
2
B
7
2
B
8
GND
2
CLKENAB
2
CLKAB
2
OEAB
GND
2
CLKENBA
2
CLKBA
2
OEBA
NOTE:
1. These pins have “Bus-Hold.” All other pins are standard inputs,
outputs, or I/Os.
FUNCTION TABLE
(1,2)
Inputs
xCLKENAB
H
X
L
L
Unit
pF
pF
pF
NEW16link
SSOP/
TSSOP/TVSOP
TOP VIEW
Outputs
xOEAB
L
L
L
L
H
xAx
X
X
L
H
X
xBx
B
0(3)
B
0(3)
L
H
Z
xCLKAB
X
L
↑
↑
X
CAPACITANCE
(T
A
= +25 C, f = 1.0MHz)
o
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
X
NOTE:
1. As applicable to the device type.
c 1998 Integrated Device Technology, Inc.
NOTES:
1. A-to-B data flow is shown: B-to-A data flow is similar but uses,
xCLKENBA, xCLKBA, and xOEBA.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑
= LOW-to-HIGH Transition
3. Level of B before the indicated steady-state input conditions were es-
tablished.
2
DSC-123456
IDT74ALVCH16952
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
– 0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
± 10
± 10
– 1.2
—
40
µA
µA
V
mV
µA
µA
V
Unit
V
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NEW16link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3
IDT74ALVCH16952
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
NEW16link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25
o
C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance
Outputs enabled
Power Dissipation Capacitance
Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
53
34
V
CC
= 3.3V ± 0.3V
Typical
71
40
Unit
pF
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
t
H
t
W
t
W
t
SK
(o)
Parameter
Propagation Delay
CLK to xAx or xBx
Output Enable Time
xOEBA to xAx or xOEAB to xBx
Output Disable Time
xOEBA to xAx or xOEAB to xBx
Setup Time, data before CLK
Hold Time, data after CLK
Setup Time,
CLKEN
before CLK
Hold Time,
CLKEN
after CLK
Pulse Duration,
CLKEN
HIGH
Pulse Duration, CLK HIGH or LOW
Output Skew
(2)
Min
.
150
1
1
1
1.7
0.6
1.2
1.1
3.3
3.3
—
Max.
—
4.1
5.4
5.3
—
—
—
—
—
—
—
V
CC
= 2.7V
Min
.
150
—
—
—
1.9
0.6
1
0.9
3.3
3.3
—
Max.
—
4.6
5.3
4.4
—
—
—
—
—
—
—
V
CC
= 3.3V ± 0.3V
Min
.
150
1
1
1.1
1.5
0.8
1
1.1
3.3
3.3
—
Max.
—
3.9
4.4
4
—
—
—
—
—
—
500
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCH16952
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V±0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
NEW16link
SAM E PHAS E
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PH L
t
PH L
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALV C Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
Generator
(1, 2)
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SW ITCH
NORM ALLY
CLOSE D
LOW
t
PZH
OUTPUT
SW ITCH
NORM ALLY
OPEN
HIGH
V
LOAD /2
V
T
t
PH Z
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD /2
V
LZ
V
OL
V
OH
V
HZ
0V
V
LOAD
Open
GND
V
IN
D.U.T.
V
OU T
R
T
500
Ω
C
L
ALV C Link
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
ALVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
t
S U
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALV C Link
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
NEW16link
t
R EM
GND
Open
TSK
t
S U
t
H
OUTPUT SKEW -
INPUT
(x)
t
PH L1
V
IH
V
T
0V
V
OH
t
PLH1
PULSE WIDTH
LOW -HIGH-LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
V
T
ALV C Link
OUTPUT 1
t
SK
(x)
t
SK
(x)
V
T
V
OL
V
OH
V
T
OUTPUT 2
t
PLH2
t
PH L2
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
P LH1
or
t
PH L2
-
t
P HL1
ALV C Link
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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