U6216A
Features
F
2048 x 8 bit static CMOS RAM
F
70 and 85 ns Access Times
F
Common data inputs and data
outputs
F
Three-state outputs
F
Typ. operating supply current
F
F
F
F
F
F
F
F
F
F
ESD protection > 2000 V
(MIL STD 883C M3015.7)
F
Latch-up immunity >100 mA
F
Packages: PDIP24 (600 mil)
Description
Standard 2K x 8 SRAM
be available at the outputs
DQ0 - DQ7. After the address
change, the data outputs go High-Z
until the new information read is
available. The data outputs have
no preferred state. If the memory is
driven by CMOS levels in the
active state, and if there is no
change of the address, data input
and control signals W or G, the
operating current (I
O
= 0 mA) drops
to the value of the operating cur-
rent in the Standby mode. The
Read cycle is finished by the falling
edge of W, or by the rising edge of
E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
SOP24 (300 mil)
70 ns: 30 mA
85 ns: 28 mA
Data retention current at 3 V:
< 10
µA
(standard)
Standby current standard < 30
µA
Standby current low power (L)
< 5
µA
Standby current for L-version at
25
°C
and 5 V: typ. 50 nA
TTL/CMOS-compatible
Automatical reduction of power-
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges
0 to 70
°C
-40 to 85
°C
CECC 90000 Quality Standard
The U6216A is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
E = L each address change leads
to a new Read or Write cycle. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word read will
Pin Configuration
Pin Description
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
VCC
A8
A9
W
G (OE)
A10
E (CE)
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
PDIP
SOP
19
18
17
16
15
14
13
Top View
December 12, 1997
1
U6216A
Block Diagram
A4
A5
A6
A7
A8
A9
A10
Row Decoder
Row Address
Inputs
Memory Cell
Array
128 Rows x
128 Columns
Column Address
Inputs
A0
A1
A2
A3
Column Decoder
DQ0
Common Data I/O
Sense Amplifier/
Write Control Logic
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Address
Change
Detector
Clock
Generator
V
CC
V
SS
E
W
G
Truth Table
Operating Mode
Standby/not selected
Internal Read
Read
Write
* H or L
E
H
L
L
L
W
*
H
H
L
G
*
H
L
*
DQ0 - DQ7
High-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
t(QX )
, in which cases transition is measured
±
200 mV from steady-state voltage.
Maximum Ratings
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating
Temperature
Storage Temperature
C-Type
K-Type
Symbol
V
CC
V
I
V
O
P
D
T
a
T
stg
2
Min.
-0.5
-0.5
-0.5
Max.
7
V
CC
+ 0.5
V
CC
+ 0.5
1
Unit
V
V
V
W
°C
°C
°C
December 12, 1997
0
-40
-55
70
85
125
U6216A
Recommended
Operating Conditions
Power Supply Voltage
Data Retention Voltage
Input Low Voltage*
Input High Voltage
* -1 V at Pulse Width 50 ns
Symbol
V
CC
V
CC(DR)
V
IL
V
IH
Conditions
Min.
4.5
2.0
-0.3
2.2
Max.
5.5
Unit
V
V
0.8
V
CC
+ 0.3
V
V
Electrical Characteristics
Supply Current - Operating Mode
Symbol
I
CC(OP)
V
CC
V
IL
V
IH
t
cW
Conditions
=
=
=
=
=
5.5 V
0.8 V
2.2 V
70 ns
85 ns
Min.
Max.
50
45
Unit
mA
mA
Supply Current - Standby Mode
(CMOS level)
Standard
Low Power (L)
Supply Current - Standby Mode
(TTL level)
Supply Current - Data Retention
Mode (Standard)
I
CC(SB)
V
CC
V
(E)
= 5.5 V
= V
CC
- 0.2 V
30
5
µA
µA
mA
µA
µA
I
CC(SB)1
V
CC
V
(E)
V
CC(DR)
V
(E)
= 5.5 V
= 2.2 V
= 3V
= 2V
= V
CC(DR)
- 0.2 V
= 4.5 V
= -1.0 mA
= 4.5 V
= 4.0 mA
= 5.5 V
= 5.5 V
= 5.5 V
= 0V
=
=
=
=
4.5 V
2.4 V
4.5 V
0.4 V
2.4
3
I
CC(DR)
10
5
Output High Voltage
Output Low Voltage
Input High Leakage Current
Input Low Leakage Current
Output High Current
Output Low Current
Output Leakage Current
High at Three-State Outputs
Low at Three-State Outputs
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
V
CC
I
OH
V
CC
I
OL
V
CC
V
IH
V
CC
V
IL
V
CC
V
OH
V
CC
V
OL
V
CC
V
OH
V
CC
V
OL
V
0.4
2
V
µA
µA
-1
mA
mA
-2
4
I
OHZ
I
OLZ
= 5.5 V
= 5.5 V
= 5.5 V
= 0V
2
-2
µA
µA
December 12, 1997
3
U6216A
Symbol
Switching Characteristics
Alt.
Time to Output in Low-Z
Cycle Time
Write Cycle Time
Read Cycle Time
Access Time
E LOW to Data Valid
G LOW to Data Valid
Address to Data Valid
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
Data Hold Time
Address Hold from End of Write
Output Hold Time from Address
Change
E HIGH to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
t
LZ
t
WC
t
RC
t
ACE
t
OE
t
AA
t
WP
t
CW
t
AS
t
CW
t
WP
t
DS
t
DH
t
AH
t
OH
t
HZCE
t
HZWE
t
HZOE
IEC
t
t(QX)
t
cW
t
cR
t
a(E)
t
a(G)
t
a(A)
t
w(W)
t
w(E)
t
su(A)
t
su(E)
t
su(W)
t
su(D)
t
h(D)
t
h(A)
t
v(A)
t
dis(E)
t
dis(W)
t
dis(G)
40
45
0
45
40
30
0
0
5
0
0
0
50
55
0
55
50
30
0
0
5
0
0
0
30
25
30
30
30
30
07
5
70
70
08
5
85
85
07
10
08
10
ns
ns
ns
Min.
Max.
Unit
70
35
70
85
45
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Mode
V
CC
V
CC(DR)
≥
2 V
2.2 V
t
DR
0V
Data Retention
t
rec
2.2 V
E
4.5 V
V
CC(DR)
- 0.2 V
≤
V
E(DR)
≤
V
CC(DR)
+ 0.3 V
Chip Deselect to Data Retention Time
Operating Recovery Time
t
DR
:
t
rec:
min 0 ns
min t
cR
4
December 12, 1997
U6216A
Test Configuration for Functional Check
5V
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
V
CC
Input level according to the
relevant test measurement
V
IH
V
IL
Simultaneous measure-
ment of all 8 output pins
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
1.0 k
V
O
100 pF
1)
E
W
G
V
SS
660
1)
In measurement of t
dis(E)
, t
dis(W)
, t
dis(G)
, t
t(QX)
the capacitance is 5 pF.
Capacitance
Input Capacitance
Output Capacitance
Conditions
V
CC
= 5.0 V
V
I
= V
SS
f
T
a
= 1 MHz
= 25
°C
Symbol
C
I
C
O
Min.
Max.
7
7
Unit
pF
pF
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
Example
U6216A
Typ
Package
D = PDIP
S = SOP
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
Access Time
07 = 70 ns
08 = 85 ns
Power Consumption
= Standard
L = Low Power
D
K
07
L
The date of manufacture is given by the 4 last digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.
December 12, 1997
5
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