PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87974-01
L
OW
S
KEW
, 1-
TO
-15,
D
IFFERENTIAL
-
TO
-LVCMOS C
LOCK
G
ENERATOR
F
EATURES
•
Fully integrated PLL
•
15 single ended 3.3V LVCMOS outputs
•
Selectable LVCMOS_CLK or differential CLK0, nCLK0 inputs
for redundant clock applications
•
LVCMOS_CLK accepts LVCMOS or LVTTL input levels
•
CLK0, nCLK0 pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency up to 125MHz
•
External feedback for ”zero delay” clock regeneration
•
Cycle-to-cycle jitter: ±100ps (typical)
•
Output skew: 350ps (maximum)
•
Bank skew: ±50ps (typical)
•
PLL reference zero delay: TBD
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS87974-01 is a low skew, low jitter 1-to-15
Differential-to-LVCMOS clock generator/zero
HiPerClockS™
delay buffer and is a member of the HiPerClockS
family of High Performance Clock Solutions from
ICS. The device has a fully integrated PLL and three
banks whose divider ratios can be independently controlled,
providing output frequency relationships of 1:1, 2:1, 3:1, 3:2,
3:2:1. In addition, the external feedback connection provides
for a wide selection of output-to-input frequency ratios. The
LVCMOS_CLK and CLK0, nCLK0 pins allow for redundant
clocking on the input and dynamically switching the PLL
between two clock sources.
,&6
Guaranteed low jitter and output skew characteristics make the
ICS87974-01 ideal for those applications demanding well de-
fined performance and repeatability.
P
IN
A
SSIGNMENT
VCO_SEL
V
DDOC
V
DDOC
V
DDOB
GND
GND
GND
QC3
QC0
QC1
QC2
QB0
nc
GND
nMR
CLK_EN
SELB
SELC
PLL_SEL
SELA
CLK_SEL
LVCMOS_CLK
CLK0
nCLK0
V
DD
V
DDA
1
2
3
4
5
6
7
8
9
52 51 50 49 48 47 46 45 44 43 42 41 40
39
38
37
36
35
34
GND
QB1
V
DDOB
QB2
GND
QB3
V
DDOB
QB4
FB_IN
GND
QFB
V
DDOFB
nc
ICS87974-01
33
32
31
30
29
28
10
11
12
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
FB_SEL0
GND
QA4
V
DDOA
QA3
GND
FB_SEL1
QA2
V
DDOA
QA1
GND
QA0
V
DDOA
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87974AY-01
www.icst.com/products/hiperclocks.html
1
REV. A FEBRUARY 13, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87974-01
L
OW
S
KEW
, 1-
TO
-15,
D
IFFERENTIAL
-
TO
-LVCMOS C
LOCK
G
ENERATOR
B
LOCK
D
IAGRAM
SELA
CLK_SEL
(Internal Pulldown)
(Internal Pulldown)
LVCMOS_CLK
(Internal Pulldown)
CLK0
(Internal Pulldown)
nCLK0
(Internal Pullup)
FB_IN
(Internal Pullup)
PLL_SEL
(Internal Pullup)
VCO_SEL
(Internal Pulldown)
÷2
0
1
PLL
0
1
÷4
0
1
÷2
÷4
÷6
0
D Q
5
QA0 - QA4
1
0
D Q
5
QB0 - QB4
1
SELB
(Internal Pulldown)
0
D Q
4
QC0 - QC3
1
SELC
(Internal Pulldown)
nMR
(Internal Pullup)
FB_SEL0
FB_SEL1
(Internal Pulldown)
0
1
÷2
0
D Q
QFB
1
(Internal Pulldown)
CLK_EN
(Internal Pullup)
87974AY-01
www.icst.com/products/hiperclocks.html
2
REV. A FEBRUARY 13, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87974-01
L
OW
S
KEW
, 1-
TO
-15,
D
IFFERENTIAL
-
TO
-LVCMOS C
LOCK
G
ENERATOR
Type
Power
Description
Power supply ground. Connect to ground.
Master reset. When HIGH, outputs are enabled.
When LOW, outputs are disabled and dividers are reset.
LVCMOS / LVTTL interface levels.
Clock enable. When LOW, all outputs except QFB are low.
Selects divide value for Bank B output as described in Table 3.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank C output as described in Table 3.
LVCMOS / LVTTL interface levels.
Selects between the PLL and the reference clock as the input to the
dividers. When HIGH, selects PLL. When LOW, selects the reference
clock. LVCMOS / LVTTL interface levels.
Selects divide value for Bank A output as described in Table 3.
LVCMOS / LVTTL interface levels.
Clock select input. LVCMOS / LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 15, 19,
24, 30,
35, 39,
43, 47, 51
2
3
4
5
6
7
8
9
10
11
27, 42
12
13
14, 20
16, 18,
21, 23, 25
17, 22, 26
28
29
31
Name
GND
nMR
CLK_EN
SELB
SELC
PLL_SEL
SELA
CLK_SEL
LVCMOS_CLK
CLK0
nCLK0
nc
V
DD
V
DDA
FB_SEL0,
FB_SEL1
QA4, QA3,
QA2, QA1, QA0
V
DDOA
V
DDOFB
QFB
FB_IN
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Unused
Power
Power
Input
Output
Power
Power
Output
Input
Output
Power
Output
Power
Input
Pullup
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input
No connect.
Positive supply pin. Connect to 3.3V.
Analog supply pin. Connect to 3.3V.
Selects divide value for Bank feedback output as described in
Pulldown
Table 3. LVCMOS / LVTTL interface levels.
Bank A clock outputs. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins. Connect to 3.3V.
Output supply pins. Connect to 3.3V.
Clock output. LVCMOS / LVTTL interface levels.
Feedback input to phase detector for generating clocks with
Pullup
"zero delay". Connect to pin 29. LVCMOS / LVTTL interface levels.
Bank B clock outputs. 7
Ω
typical output impedance.
LVCMOS interface levels.
Output supply pins. Connect to 3.3V.
Bank C clock outputs. 7
Ω
typical output impedance.
LVCMOS interface levels.
Output supply pins. Connect to 3.3V.
Selects VCO ÷ 4 when HIGH. Selects VCO ÷ 2 when LOW.
Pulldown
LVCMOS / LVTTL interface levels.
32, 34,
QB4, QB3,
36, 38, 40 QB2, QB1, QB0
33, 37, 41
V
DDOB
44, 46,
QC3, QC2,
48, 50
QC1, QC0
45, 49
V
DDOC
52
VCO_SEL
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87974AY-01
www.icst.com/products/hiperclocks.html
3
REV. A FEBRUARY 13, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87974-01
L
OW
S
KEW
, 1-
TO
-15,
D
IFFERENTIAL
-
TO
-LVCMOS C
LOCK
G
ENERATOR
Test Conditions
Minimum
Typical
51
51
V
DD,
V
DDA
,
*V
DDOx
= 3.465V
15
Maximum
4
Units
pF
KΩ
KΩ
pF
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
C
PD
(per output)
*
NOTE: V
DDOx
denotes V
DDOA
, V
DDOB
, V
DDOC
, V
DDOFB
.
T
ABLE
3A. O
UTPUT
C
ONTROL
P
IN
F
UNCTION
T
ABLE
Inputs
nMR
0
1
1
CLK_EN
X
0
1
QA0 - QA4
HiZ
LOW
Enable
QB0 - QB4
HiZ
LOW
Enable
Outputs
QC0 - QC3
HiZ
LOW
Enable
QFB
HiZ
Enable
Enable
T
ABLE
3B. O
PERATING
M
ODE
F
UNCTION
T
ABLE
Inputs
PLL_SEL
0
1
Operating Mode
Bypass
PLL
T
ABLE
3C. PLL I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_SEL
0
1
PLL Input
LVCMOS_CLK
CLK0, nCLK0
T
ABLE
3D. S
ELECT
P
IN
F
UNCTION
T
ABLE
SELA
0
1
QAx
÷2
÷4
SELB
0
1
QBx
÷2
÷4
SELC
0
1
QCx
÷4
÷6
T
ABLE
3E. FB S
ELECT
F
UNCTION
T
ABLE
Inputs
FB_SEL0
0
0
1
1
FB_SEL1
0
1
0
1
Outputs
QFB
÷4
÷6
÷8
÷ 12
T
ABLE
3F. VCO S
ELECT
F
UNCTION
T
ABLE
Inputs
VCO_SEL
0
1
fVCO
VCO/2
VCO/4
87974AY-01
www.icst.com/products/hiperclocks.html
4
REV. A FEBRUARY 13, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87974-01
L
OW
S
KEW
, 1-
TO
-15,
D
IFFERENTIAL
-
TO
-LVCMOS C
LOCK
G
ENERATOR
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
X
Symbol
V
DD
V
DDA
*V
DDOx
I
DD
I
DDO
I
DDA
Parameter
Positive Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
90
10
290
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
*
NOTE: V
DDOx
denotes V
DDOA
, V
DDOB
, V
DDOC
, V
DDOFB
.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
X
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
FB_SEL0, FB_SEL1,
SELA, SELB, SELC,
CLK_SEL, VCO_SEL
Input High Current
LVCMOS_CLK
FB_IN, nMR,
PLL_SEL, CLK_EN
FB_SEL0, FB_SEL1,
SELA, SELB, SELC,
CLK_SEL, VCO_SEL
Input Low Current
LVCMOS_CLK
FB_IN, nMR,
PLL_SEL, CLK_EN
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Tristate Current Low
Output Tristate Current High
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
V
DD
= V
IN
= 3.465V
I
IH
V
DD
= V
IN
= 3.465V
5
µA
V
IN
= 0V, V
DD
= 3.465V
-5
µA
I
IL
V
IN
= 0V, V
DD
= 3.465V
-150
2.4
0.5
TBD
TBD
µA
V
V
µA
µA
V
OH
V
OL
I
OZL
I
OZH
NOTE 1: Outputs terminated with 50
Ω
to V
DDOx
/2.
87974AY-01
www.icst.com/products/hiperclocks.html
5
REV. A FEBRUARY 13, 2002
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