PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
LVHSTL F
ANOUT
B
UFFER
F
EATURES
•
4 LVHSTL outputs each with the ability to drive 50Ω to ground
•
Selectable differential HSTL or PECL clock inputs
•
Voh (max) = 1.2V
•
Input crossover voltage, Vx, 0.68V
≤
Vx
≤
0.9V
•
Output frequency up to 500MHz
•
30ps output skew
•
3.3V input, 1.8V output operating supply voltages
•
LVCMOS / LVTTL control inputs
•
20 lead TSSOP
•
0°C to 70°C ambient operating temperature
•
Industrial temperature version available upon request
G
ENERAL
D
ESCRIPTION
The ICS8523 is a low skew, high performance,
1-to-4 LVHSTL clock fanout buffer and a member
HiPerClockS™
of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS8523 has
selectable clock inputs that accept either HSTL
or PECL input levels. The clock enable is synchronous which
eliminates the runt clock pulses which occur during asynchro-
nous enabling and disabling of the outputs.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS8523 ideal for those applications demanding
well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
nD
Q
LE
HCLK
nHCLK
PCLK
nPCLK
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
P
IN
A
SSIGNMENT
VEE
CLK_EN
CLK_SEL
HCLK
nHCLK
PCLK
nPCLK
nc
nc
VDDI
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
VDDO
Q1
nQ1
Q2
nQ2
VDDO
Q3
nQ3
CLK_SEL
ICS8523
20-Lead TSSOP
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
8523
www.icst.com
REV. C FEBRUARY 9, 2001
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
LVHSTL F
ANOUT
B
UFFER
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8, 9
10
11, 12
13, 18
14, 15
16, 17
19, 20
Name
VEE
CLK_EN
CLK_SEL
HCLK
nHCLK
PCLK
nPCLK
nc
VDDI
nQ3, Q3
VDDO
nQ2, Q2
nQ1, Q1
nQ0, Q0
Power
Input
Input
Input
Input
Input
Input
Unused
Power
Output
Power
Output
Output
Output
Type
Negative power supply pin. Connect to power supply ground.
Synchronous clock enable. When HIGH clock outputs follows clock input.
Pullup
When LOW, Q outputs are force low, nQ outputs are force high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH selects differential HSTL inputs.
Pulldown
When LOW selects differential PECL inputs. LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential HSTL clock input.
Pullup
Inver ting differential HSTL clock input.
Pulldown Non-inver ting differential PECL clock input.
Pullup
Inver ting differential PECL clock input.
Unused pins.
Input power supply pin. Connect to 3.3V.
Differential clock outputs. LVHSTL interface
Output power supply. Connect to 1.8V.
Differential clock outputs. LVHSTL interface
Differential clock outputs. LVHSTL interface
Differential clock outputs. LVHSTL interface
levels.
levels.
levels.
levels.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
Parameter
HCLK, nHCLK
CIN
Input
Capacitance
PCLK, nPCLK
CLK_EN,
CLK_SEL
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
Maximum
Units
pF
pF
pF
51
51
KΩ
KΩ
RPULLUP
RPULLDOWN
8523
www.icst.com
2
REV. C FEBRUARY 9, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
LVHSTL F
ANOUT
B
UFFER
Outputs
CLK_SEL
0
1
0
Q0 thru Q3
LOW
LOW
Active
nQ0 thru nQ3
HIGH
HIGH
Active
T
ABLE
3A. C
ONTROL
I
NPUTS
F
UNCTION
T
ABLE
Inputs
CLK_EN
0
0
1
1
1
Active
Active
In the active mode the state of the output is a function of the HCLK , nHCLK and PCLK, nPCLK inputs as described
in Table 3B.
T
ABLE
3B. C
LOCK
I
NPUTS
F
UNCTION
T
ABLE
Inputs
HCLK or PCLK
0
1
0
1
Biased; NOTE 1
nHCLK or
nPCLK
0
1
Biased; NOTE 1
Biased; NOTE 1
0
Outputs
Q0 thru Q3
LOW
HIGH
LOW
HIGH
HIGH
nQ0 thru nQ3
HIGH
LOW
HIGH
LOW
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1: Single ended use requires that one of the differential input be biased. The voltage at the biased input sets the
switch point for the single ended input. For LVCMOS and LVTTL levels the recommended input bias network is a 10K
Ω
resistor from the input pin to VDD, 10K
Ω
resistor from the input pin to ground and a 0.1µF capacitor from the input to
ground. The resulting switch point is VDD/2 ± 300mV.
8523
www.icst.com
3
REV. C FEBRUARY 9, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
LVHSTL F
ANOUT
B
UFFER
4.6V
-0.5V to VDDI + 0.5V
-0.5V to VDDO + 0.5V
0°C to 70°C
-65°C to 150°C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage
Inputs
Outputs
Ambient Operating Temperature
Storage Temperature
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of product at these condition or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
VDDI = 3.3V±5%, VDDO = 1.8V±10%, T
A
=0°C
TO
70°C
Symbol
VDDI
VDDO
IEE
Parameter
Input Power Supply Voltage
Ouptut Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
50
Units
V
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
VDDI = 3.3V±5%, VDDO = 1.8V±10%, T
A
=0°C
TO
70°C
Symbol
VIH
VIL
IIH
IIL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_EN, CLK_SEL
CLK_EN, CLK_SEL
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
3.765
0.8
5
150
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
VDDI = 3.3V±5%, VDDO = 1.8V±10%, T
A
=0°C
TO
70°C
Symbol
IIH
Parameter
PCLK
Input High Current
nPCLK
IIL
VPP
Input Low Current
PCLK
nPCLK
Peak-to-Peak Input Voltage
-5
-150
0.1
1.3
5
µA
µA
µA
V
Test Conditions
Minimum
Typical
Maximum
150
Units
µA
VCMR
Common Mode Input Voltage; NOTE 1
0.13
1.3
V
NOTE 1: Common mode voltage for PECL is defined as the minimum VIH. VCMR is compatible with DCM, LVDS, LVPECL
and SSTL input levels.
8523
www.icst.com
4
REV. C FEBRUARY 9, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
LVHSTL F
ANOUT
B
UFFER
Test Conditions
HCLK
nHCLK
HCLK
nHCLK
-5
-150
0.1
0.13
1.0
1.3
1.3
1.2
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
V
V
V
T
ABLE
4D. LVHSTL DC C
HARACTERISTICS
,
VDDI = 3.3V±5%, VDDO = 1.8V±10%, T
A
=0°C
TO
70°C
Symbol Parameter
IIH
IIL
VPP
VCMR
VOH
VOL
Input High Current
Input Low Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
0
0.4
40% x
60% x
VOX
Output Crossover Voltage
(VOH-VOL)
(VOH-VOL)
+ VOL
+ VOL
NOTE 1: Common mode voltage for HSTL is defined as the crossover voltage. VCMR is compatible with DCM,
LVDS, LVPECL and SSTL input levels.
NOTE 2: For single ended applications the maximum input voltage for HCLK and nHCLK is VDD + 0.3V.
NOTE 3: Outputs terminated with 50
Ω
to ground. The power dissipation of a terminated output pair is 32mW.
T
ABLE
5. E
LECTRICAL
AC C
HARACTERISTICS
,
VCC=3.3V±5%, VCCO=1.8V±10%, T
A
=0°C
TO
70°C
Symbol
fMAX
tpLH
tpHL
tsk(o)
tsk(pp)
tjit(Ø)
tR
tF
tPW
tS
Parameter
Maximum Input Frequency
Propagation Delay, Low-to-High; NOTE 2
Propagation Delay, High-to-Low; NOTE 2
Output Skew; NOTE 3
Par t-to-Par t; NOTE 4
Input-to-Output Jitter ; NOTE 5
Output Rise Time
Output Fall Time
Output Pulse Width
Clock Enable Setup Time
30% to 70%
30% to 70%
100
100
tCYCLE/2
-TBD
1.0
1.0
1.0
Test Conditions
Minimum
Typical
Maximum
650
2.0
2.0
30
150
0
800
800
tCYCLE/2
+TBD
Units
MHz
ns
ns
ps
ps
ps
ps
ps
ns
ns
ns
tCYCLE/2
tH
Clock Enable Hold Time
1.0
NOTE 1: All parameters measured at 500Mhz unless noted otherwise.
NOTE 2: Measured from the 50% point to the differential output crossing point.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from the 50% point of the input to the differential output crossing point.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Measured from the 50% point of like inputs to the differential output crossing point.
NOTE 5: Measured by triggering on input signal and measuring the largest displacement between output cycles.
8523
www.icst.com
5
REV. C FEBRUARY 9, 2001
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