UL62H1616A
Low Voltage Automotive Fast 64K x 16 SRAM
Features
!
65536 x 16 bit static CMOS RAM
!
15, 20 and 35 ns Access Time
!
Common data inputs and
!
!
!
!
!
Description
The UL62H1616A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Lower / Upper Byte Read
- Word Read
- Lower / Upper Byte Write
- Word Write
- Standby
- Data Retention
The memory array is based on a
6-Transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
E = L and W = H each address
change leads to a new Read cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G. If LB = L the data lower byte will
be available at the outputs DQ0-
DQ7, on UB = L the data upper
byte appear at the outputs DQ8-
DQ15. After the address change,
the data outputs go High-Z until the
new information is available. The
data outputs have no preferred
state. The Read cycle is finished by
the falling edge of W, or by the
rising edge of E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
!
!
!
!
data outputs
Three-state outputs
Standby current < 150 µA
at 125°C
TTL/CMOS-compatible
Power supply voltage 3.3 V
Operating temperature range
K-Type:-40 °C to 85 °C
A-Type:-40 °C to 125 °C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity >100 mA
Package: TSOP II 44 (400 mil)
Pin Configuration
A4
A3
A2
A1
A0
E
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
W
A15
A14
A13
A12
n.c.
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
36
9
35
10
34
11
TSOPII
33
12
32
13
31
14
15
30
29
16
28
17
18
27
19
26
20
25
21
24
22
23
A5
A6
A7
G
UB
LB
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
n.c.
A8
A9
A10
A11
n.c.
Pin Description
BGA
LB
DQ8
DQ9
VSS
VCC
G
UB
DQ10
DQ11
DQ12
A0
A3
A5
n.c.
n.c.
A14
A12
A9
A1
A4
A6
A7
n.c.
A15
A13
A10
A2
E
DQ1
DQ3
DQ4
DQ5
W
A11
n.c.
DQ0
DQ2
VCC
VSS
DQ6
DQ7
n.c.
Signal Name Signal Description
A0 - A15
DQ0 - DQ15
E
G
W
UB
LB
VCC
VSS
n.c.
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Upper Byte Enable
Lower Byte Enable
Power Supply Voltage
Ground
not connected
DQ14 DQ13
DQ15
n.c.
n.c.
A8
Top View
Top View
April 21, 2004
1
UL62H1616A
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 2.5 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured ±200 mV from steady-state voltage.
Absolute Maximum Ratings
a
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
Output Short-Circuit Current
at V
CC
= 3.3 V and V
O
= 0 V
c
a
Symbol
V
CC
V
I
V
O
P
D
Min.
-0.3
-0.5
-0.5
-
-40
-40
-65
Max.
4.6
V
CC
+ 0.5
b
V
CC
+ 0.5
b
1
85
125
150
100
Unit
V
V
V
W
°C
°C
mA
K-Type
A-Type
T
a
T
stg
| I
OS
|
b
c
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
Maximum voltage is 4.6 V
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Recommended
Operating Conditions
Power Supply Voltage
Input Low Voltage
d
Input High Voltage
d
Symbol
V
CC
V
IL
V
IH
Conditions
Min.
3.0
-0.3
2.0
Max.
3.6
0.8
V
CC
+ 0.3
Unit
V
V
V
-2 V at Pulse Width 10 ns
April 21, 2004
3
UL62H1616A
Switching Characteristics
Read Cycle
Read Cycle Time
Address Access Time to Data Valid
Chip Enable Access Time to Data Valid
G LOW to Data Valid
LB, UB LOW to Data Valid
E HIGH to Output in High-Z
G HIGH to Output in High-Z
LB, UB HIGH to Output in High-Z
E LOW to Output in Low-Z
G LOW to Output in Low-Z
LB, UB LOW to Output in Low-Z
Output Hold Time from Address Change
E LOW to Power-Up Time
E HIGH to Power-Down Time
Symbol
Alt.
t
RC
t
AA
t
ACE
t
OE
t
B
t
HZCE
t
HZOE
t
HZB
t
LZCE
t
LZOE
t
LZB
t
OH
t
PU
t
PD
Symbol
Alt.
t
WC
t
WP
t
WP
t
AS
t
AW
t
CW
t
BW
t
CW
t
BW
t
DS
t
DH
t
AH
t
HZWE
t
HZOE
t
LZWE
t
LZOE
IEC
t
cW
t
w(W)
t
su(W)
t
su(A)
t
su(A-WH)
Min.
15
Min.
Max.
Min.
20
Max.
Min.
35
Max.
IEC
t
cR
t
a(A)
t
a(E)
t
a(G)
t
a(B)
t
dis(E)
t
dis(G)
t
dis(B)
t
en(E)
t
en(G)
t
en(B)
t
v(A)
Unit
ns
35
35
15
15
12
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
ns
15
15
15
7
7
7
7
7
4
0
0
3
0
15
15
Max.
20
20
20
9
9
8
8
8
4
0
0
3
0
20
20
Min.
Max.
35
5
0
0
3
0
Switching Characteristics
Write Cycle
Write Cycle Time
Write Pulse Width
Write Setup Time
Address Setup Time
Address Valid to End of Write
Chip Enable Setup Time
Byte Enable Setup Time
Pulse Width Chip Enable to End of Write
Pulse Width Byte Enable to End of Write
Data Setup Time
Data Hold Time
Address Hold from End of Write
W LOW to Output in High-Z
G HIGH to Output in High-Z
W HIGH to Output in Low-Z
G LOW to Output in Low-Z
35
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
12
ns
ns
ns
ns
15
10
10
0
10
10
10
10
10
7
0
0
7
7
3
0
20
12
12
0
12
12
12
12
12
9
0
0
8
8
3
0
35
20
20
0
20
25
25
25
25
15
0
0
t
su(E)
t
su(B)
t
w(E)
t
w(B)
t
su(D)
t
h(D)
t
h(A)
t
dis(W)
t
dis(G)
t
en(W)
t
en(G)
3
0
April 21, 2004
5
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