ICS9112CM-18 datasheet, PDF - EEWORLD Datasheet

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ICS9112CM-18: DescriptionPLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, SOIC-16; Categorylogic logic; File Size78KB，5 Pages; ManufacturerIDT (Integrated Device Technology)

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ICS9112CM-18 Overview

PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, SOIC-16

ICS9112CM-18 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOIC
package instruction	SOP,
Contacts	16
Reach Compliance Code	compliant
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	9.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	16
Actual output times	8
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm
minfmax	160 MHz

ICS9112CM-18 Preview

MK2308-2

ERO

ELAY

, L

KEW

UFFER

Description

The MK2308-2 is a low jitter, low skew, high

performance Phase-Lock Loop (PLL) based zero delay

buffer for high speed applications. Based on ICS’

proprietary low jitter PLL techniques, the device

provides eight low skew outputs at speeds up to 160

MHz at 3.3 V. The MK2308-2 includes a bank of four

outputs running at 1/2X. In the zero delay mode, the

rising edge of the input clock is aligned with the rising

edges of all eight outputs. Compared to competitive

CMOS devices, the MK2308-2 has the lowest jitter.

Features

•

Packaged in 16-pin SOIC

Zero input-output delay

Four 1X outputs plus four 1/2X outputs

Output to output skew is less than 250 ps

Output clocks up to 160 MHz at 3.3 V

Ability to generate 2X the input

Full CMOS outputs with 18 mA output drive

capability at TTL levels at 3.3 V

spectrum clock generators

•

Spread Smart

technology works with spread

•

Advanced, low power, sub micron CMOS process

•

Operating voltage of 3.3 V or 5 V

Block Diagram

VDD

CLKA1

FBIN

CLKIN

CLKA2

CLKA3

CLKA4

BANK

PLL

CLKB1

CLKB2

S2, S1

Control

Logic

CLKB3

CLKB4

BANK

GND

MDS 2308-2 B

I n t e gra te d C i r c u i t S y s t e m s

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525 Race Stre et, San Jo se, CA 9 5126

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MK2308-2

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Pin Assignment

CLKIN

CLKA1

CLKA2

VDD

GND

CLKB1

CLKB2

FBIN

CLKA4

CLKA3

VDD

GND

CLKB4

CLKB3

Feedback Configuration Table

Feedback From

Bank A

Bank B

CLKA1:A4

CLKIN

2XCLKIN

CLKB1:B4

CLKIN/2

CLKIN

16-pin (150 mil) SOIC

Output Clock Mode Select Table

Clocks A1:A4

Tri-state (high impedance)

Running

Clocks B1:B4

Tri-state (high impedance)

Running

Internet Generation

None

PLL

Buffer only (no zero delay)

PLL

PLL Status

Off

Pin Descriptions

Number

2-3

6-7

10 - 11

14 - 15

Name

CLKIN

CLKA1:A4

VDD

GND

CLKB1:B4

GND

VDD

CLKA1:A4

FBIN

Type

Input

Output

Power

Output

Input

Output

Power

Output

Input

Pin Description

Clock input. Connect to input clock source.

Clock A bank of four outputs.

Power supply. Connect pin to same voltage as pin 13 (either 3.3 V or 5 V).

Connect to ground.

Clock B bank of four outputs. These are low skew divide by two of bank A.

Select input 2. Selects mode for outputs per table above.

Select input 1. Selects mode for outputs per table above.

Clock B bank of four outputs. These are low skew divide by two of bank A.

Connect to ground.

Power supply. Connect pin to same voltage as pin 4 (either 3.3 V or 5 V).

Clock A bank of four outputs.

Feedback input. Determines outputs per table above.

MDS 2308-2 B

In te grated Circuit Systems

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525 Ra ce Street, San Jose, CA 9512 6

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MK2308-2

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External Components

The MK2308-2 requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.1µF should be connected between VDD and GND, as close to the part as possible. A 33Ω

series terminating resistor should be used on each clock output to reduce reflections.

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the MK2308-2. These ratings,

which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of

the device at these or any other conditions above those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can

affect product reliability. Electrical parameters are guaranteed only over the recommended operating

temperature range.

Item

Supply Voltage, VDD

All Inputs and Outputs

Ambient Operating Temperature

Storage Temperature

Junction Temperature

Soldering Temperature

Rating

-0.5 V to VDD+0.5 V

0 to +70

°C

-65 to +150

°C

175

°C

260

°C

Recommended Operation Conditions

Parameter

Ambient Operating Temperature

Power Supply Voltage (measured in respect to GND)

Min.

+3.0

Typ.

Max.

+70

+5.5

Units

°C

DC Electrical Characteristics

VDD=3.3 V ±10%,

Temp 0 to +70°

/-40

to +85° C

Parameter

Operating Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

Symbol

VDD

Conditions

CLKIN pin only

Min.

3.0

(VDD/2)+1

Typ.

VDD/2

Max.

5.5

(VDD/2)-1

0.8

Units

= -18 mA

= 18 mA

= -5 mA

2.4

0.4

VDD-0.4

MDS 2308-2 B

In te grated Circuit Systems

●

525 Ra ce Street, San Jose, CA 9512 6

●

Revision 111103

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MK2308-2

ERO

ELAY

, L

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UFFER

Parameter

Operating Supply Current

100 MHz, CLKIN

Short Circuit Current

Input Capacitance

Symbol

IDD

Conditions

No Load

S1=S2=1

Each output

S1, S1, FBIN

Min.

Typ.

± 65

Max.

Units

AC Electrical Characteristics

VDD = 3.3V ±10%,

Temp 0 to +70°/ -40 to +85° C

Parameter

Input Frequency

Output Frequency

Output Rise Time

Output Fall Time

Output Clock Duty Cycle

Device to Device skew, equally

loaded

Output to Output skew, equally

loaded

Maximum Absolute Jitter

Cycle to Cycle Jitter

Symbol

Conditions

FBIN to CLKA1

S1=S2=1

FBIN to CLKA1

S1=S2=1

Min.

Typ.

Max. Units

160

1.5

MHz

400

±250

0.8 to 2.0 V, C

=30 pF

0.8 to 2.0 V, C

=30 pF

at 1.4V

rising edges at VDD/2

300

30 pF loads

66.67 MHz outputs

15 pF loads

66.67 MHz outputs

700

200

Skew from Output Bank A to

Output Bank B

Delay CLKIN Rising Edge to

FBIN Rising Edge

PLL Lock Time

LOCK

All outputs equally

loaded

measured at VDD/2

Stable power supply,

valid clocks on CLKIN,

FBIN

Thermal Characteristics

Parameter

Thermal Resistance Junction to

Ambient

Symbol

Conditions

Still air

1 m/s air flow

3 m/s air flow

Min.

Typ.

120

115

105

Max. Units

°C/W

Thermal Resistance Junction to Case

MDS 2308-2 B

In te grated Circuit Systems

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525 Ra ce Street, San Jose, CA 9512 6

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Revision 111103

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MK2308-2

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Package Outline and Package Dimensions

(16-pin SOIC, 150 Mil. Narrow Body)

Package dimensions are kept current with JEDEC Publication No. 95

Millimeters

Symbol

Min

Max

Inches

Min

Max

INDEX

AREA

1 2

1.35

1.75

0.10

0.25

0.33

0.51

0.19

0.25

9.80

10.00

3.80

4.00

1.27 BASIC

5.80

6.20

0.25

0.50

0.40

1.27

.0532

.0688

.0040

.0098

.013

.020

.0075

.0098

.3859

.3937

.1497

.1574

0.050 BASIC

.2284

.2440

.010

.020

.016

.050

h x 45

-C-

SEATING

PLANE

.10 (.004)

Ordering Information

Part / Order Number

MK2308S-2

MK2308S-2T

MK2308S-2I

MK2308S-2IT

Marking

MK2308S-2

MK2308S-2T

MK2308S-2I

MK2308S-2IT

Shipping

packaging

Tubes

Tape and Reel

Tubes

Tape and Reel

Package

16-pin SOIC

Temperature

0 to 70° C

-40 to +85° C

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit

Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of

third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is

intended for use in normal commercial applications. Any other applications such as those requiring extended

temperature range, high reliability, or other extraordinary environmental requirements are not recommended

without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice.

ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

MDS 2308-2 B

In te grated Circuit Systems

●

525 Ra ce Street, San Jose, CA 9512 6

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Revision 111103

tel (4 08) 297-1 201

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w w w. i c s t . c o m

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