U62H256AS1K55LLG1 datasheet, PDF

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U62H256AS1K55LLG1: DescriptionStandard SRAM, 32KX8, 55ns, CMOS, PDSO28, 0.330 INCH, SOP-28; Categorystorage storage; File Size84KB，9 Pages; ManufacturerZentrum Mikroelektronik Dresden AG (IDT); Environmental Compliance

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U62H256AS1K55LLG1 Overview

Standard SRAM, 32KX8, 55ns, CMOS, PDSO28, 0.330 INCH, SOP-28

U62H256AS1K55LLG1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Zentrum Mikroelektronik Dresden AG (IDT)
Parts packaging code	SOIC
package instruction	SOP,
Contacts	28
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	55 ns
JESD-30 code	R-PDSO-G28
JESD-609 code	e3
length	18.1 mm
memory density	262144 bit
Memory IC Type	STANDARD SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	28
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32KX8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	2.54 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	8.75 mm

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U62H256A

Automotive Fast 32K x 8 SRAM

Features

32768 x 8 bit static CMOS RAM

35 and 55 ns Access Time

Common data inputs and

Description

go High-Z until the new information

is available. The data outputs have

no preferred state. The Read cycle

is finished by the falling edge of W,

or by the rising edge of E, respec-

tively.

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

The U62H256A is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

data outputs

- Read

- Standby

Three-state outputs

- Write

- Data Retention

Typ. operating supply current

The memory array is based on a

35 ns: 45 mA

6-transistor cell.

55 ns: 30 mA

Standby current < 50 µA at 125 °C The circuit is activated by the fal-

ling edge of E. The address and

TTL/CMOS-compatible

control inputs open simultaneously.

Power supply voltage 5 V

According to the information of W

Operating temperature range

-40 °C to 85 °C

and G, the data inputs, or outputs,

-40 °C to 125 °C

are active. In a Read cycle, the

data outputs are activated by the

CECC 90000 Quality Standard

falling edge of G, afterwards the

ESD protection > 2000 V

(MIL STD 883C M3015.7)

data word will be available at the

outputs DQ0-DQ7. After the

Latch-up immunity >100 mA

address change, the data outputs

Package: SOP28 (300/330 mil)

Pin Configuration

Pin Description

A14

A12

DQ0

DQ1

DQ2

VSS

VCC

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

Signal Name

A0 - A14

DQ0 - DQ7

VCC

VSS

Signal Description

Address Inputs

Data In/Out

Chip Enable

Output Enable

Write Enable

Power Supply Voltage

Ground

SOP

Top View

July 10, 2002

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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