Error Detection And Correction Circuit, CMOS Series, 16-Bit, CMOS, CDIP48, 0.600 INCH, 2.54 MM PITCH, SIDE BRAZED, DIP-48
| Parameter Name | Attribute value |
| Is it lead-free? | Contains lead |
| Is it Rohs certified? | incompatible |
| Maker | IDT (Integrated Device Technology) |
| Parts packaging code | DIP |
| package instruction | DIP, DIP48,.6 |
| Contacts | 48 |
| Reach Compliance Code | not_compliant |
| Other features | BUILT IN DIAGNOSTICS; BYTE CONTROL |
| series | CMOS |
| JESD-30 code | R-CDIP-T48 |
| JESD-609 code | e0 |
| length | 60.96 mm |
| Load capacitance (CL) | 50 pF |
| Logic integrated circuit type | ERROR DETECTION AND CORRECTION CIRCUIT |
| Number of digits | 16 |
| Number of functions | 1 |
| Number of terminals | 48 |
| Maximum operating temperature | 125 °C |
| Minimum operating temperature | -55 °C |
| Output characteristics | 3-STATE |
| Package body material | CERAMIC, METAL-SEALED COFIRED |
| encapsulated code | DIP |
| Encapsulate equivalent code | DIP48,.6 |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| propagation delay (tpd) | 73 ns |
| Certification status | Not Qualified |
| Filter level | 38535Q/M;38534H;883B |
| Maximum seat height | 4.826 mm |
| Maximum supply voltage (Vsup) | 5.5 V |
| Minimum supply voltage (Vsup) | 4.5 V |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | MILITARY |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| width | 15.24 mm |
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