K1B3216B8E
Preliminary
UtRAM
32Mb (2M x 16 bit) UtRAM
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IS SUBJECT TO CHANGE WITHOUT NOTICE.
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OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN
SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUAR-
ANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
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* Samsung Electronics reserves the right to change products or specification without notice.
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Revision 0.1
January 2007
K1B3216B8E
Document Title
Preliminary
UtRAM
2Mx16 bit Multiplexed Synchronous Burst Uni-Transistor Random Access Memory
Revision History
Revision No.
0.0
History
Initial
- Design target
Draft Date
December 19, 2006
Remark
Preliminary
0.1
Revised
- Inserted package dimension
January 11, 2007
Preliminary
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Revision 0.1
January 2007
K1B3216B8E
Table of Contents
Preliminary
UtRAM
GENERAL DESCRIPTION...............................................................................................................................1
FEATURES ......................................................................................................................................................1
PRODUCT FAMILY..........................................................................................................................................1
PIN DESCRIPTIONS & FUNCTION BLOCK DIAGRAM..................................................................................2
TERMINOLOGY DESCRIPTION .....................................................................................................................2
POWER UP SEQUENCE.................................................................................................................................3
MODE STATE MACHINE.................................................................................................................................3
ABSOLUTE MAXIMUM RATINGS ...................................................................................................................4
RECOMMENDED DC OPERATING CONDITIONS.........................................................................................4
CAPACITANCE ................................................................................................................................................4
DC AND OPERATING CHARACTERISTICS...................................................................................................4
MRS (MODE REGISTER SET) ........................................................................................................................5
MRS CODE ................................................................................................................................................ 5
MRS TIMING WAVEFORM (SOFTWARE) ................................................................................................ 6
PAR (Partial Array Refresh) mode A/DQ[3]~A/DQ[0] ................................................................................. 7
DPD (Deep Power Down) mode A/DQ[4] ................................................................................................... 7
Burst Length A/DQ[7]~A/DQ[5] & Wrap A/DQ[12] ...................................................................................... 8
WAIT Configuration A/DQ[8] & WAIT Polarity A/DQ[13] ............................................................................ 8
Latency A/DQ[11]~A/DQ[9]......................................................................................................................... 9
Driver Strength A/DQ[17]~A/DQ[16] ........................................................................................................... 9
OPEARTION MODE (A/DQ[15]~A/DQ[14])............................................................................................... 10
MODE1. ASYNCHRONOUS READ / ASYNCHRONOUS WRITE MODE ................................................. 10
MODE2. SYNCHRONOUS BURST READ / ASYNCHRONOUS WRITE MODE ...................................... 11
MODE3. SYNCHRONOUS BURST READ / SYNCHRONOUS BURST WRITE MODE ........................... 12
MODE 1 AC OPERATING CONDITIONS (ASYNCH. READ / ASYNCH. WRITE) ..........................................13
TIMING WAVEFORMS (ASYNCH. READ / ASYNCH. WRITE)................................................................. 14
Asynch. READ ............................................................................................................................................ 14
Asynchronous WRITE ................................................................................................................................ 15
MODE 2 AC OPERATING CONDITIONS (SYNCH. READ / ASYNCH. WRITE) ............................................16
TIMING WAVEFORMS (SYNCH. READ / SYNCH. WRITE) ..................................................................... 17
Burst READ - Fixed Latency....................................................................................................................... 17
Burst READ - Variable Latency .................................................................................................................. 18
Burst READ STOP...................................................................................................................................... 19
Asynch. WRITE .......................................................................................................................................... 20
Burst READ followed by Asynch. WRITE ................................................................................................... 21
Asynch. WRITE followed by Burst READ ................................................................................................... 22
MODE3. AC OPERATING CONDITIONS (SYNCH. READ / SYNCH. WRITE) ...............................................23
TIMING WAVEFORMS (SYNCH. READ / SYNCH. WRITE) ..................................................................... 24
Burst READ - Fixed Latency....................................................................................................................... 24
Burst READ - Variable Latency .................................................................................................................. 25
Burst READ STOP...................................................................................................................................... 26
Burst WRITE............................................................................................................................................... 27
Burst WRITE (ADV PULSE Interrupt)......................................................................................................... 28
Burst READ STOP & Burst WRITE STOP ................................................................................................. 29
Burst READ followed by Burst WRITE ....................................................................................................... 30
Burst WRITE followed by Burst READ ....................................................................................................... 31
PACKAGE DIMENSION...................................................................................................................................32
54 BALL FINE PITCH BGA(0.75mm ball pitch).......................................................................................... 32
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Revision 0.1
January 2007
K1B3216B8E
Preliminary
UtRAM
2M x 16 bit Multiplexed Synchronous Burst Uni-Transistor CMOS RAM
GENERAL DESCRIPTION
The world is moving into the mobile multi-media era and therefore the mobile handsets need bigger & faster memory capacity to
handle the multi-media data. SAMSUNG’s UtRAM products are designed to meet all the request from the various customers who
want to cope with the fast growing mobile market. UtRAM is the perfect solution for the mobile market with its low cost, high den-
sity and high performance feature. K1B3216B8E is fabricated by SAMSUNG′s advanced CMOS technology using one transistor
memory cell. The device supports the traditional SRAM like asynchronous operation (asynchronous page read and asynchronous
write), the NOR flash like synchronous operation (synchronous burst read and asynchronous write) and the fully synchronous
operation (synchronous burst read and synchronous burst write). These three operation modes are defined through the mode reg-
ister setting. The device also supports the special features for the standby power saving. Those are the Partial Array
Refresh(PAR) mode, Deep Power Down(DPD) mode and internal TCSR (Temperature Compensated Self Refresh). The optimiza-
tion of output drive strength is possible through the mode register setting to adjust for the different data loadings. Through this
drive strength optimization, the device can minimize the noise generated on the data bus during read operation.
FEATURES
• Process technology: CMOS
• Organization: 2M x 16 bit
• Multiplexed Address and Data bus
• Power supply voltage: 1.7V~1.95V
• Three state outputs
• Supports MRS (Mode Register Set)
- Software set up
• Supports power saving modes
- PAR (Partial Array Refresh)
- DPD (Deep Power Down)
- Internal TCSR (Temperature Compensated Self Refresh)
• Supports driver strength optimization
• K1B3216B8E supports
- Asynchronous read/ Asynchronous write
- Synchronous burst read / Asynchronous write
- Synchronous burst read / Synchronous burst write
• Synchronous burst operation
- Max. clock frequency : 104MHz
- Fixed and Variable read latency
- 4 / 8 / 16 / 32 and Continuous burst
- Wrap / No-wrap
- Latency :4(Variable) @ 104MHz
3(Variable) @ 80MHz
2(Variable) @ 66MHz
- Burst stop
- Burst read suspend
- Burst write data masking
PRODUCT FAMILY
Current Consumption
Product Family
Operating
Mode
1)
Operating Temp.
Vcc Range
Speed
Standby
(I
SB1
, Max.)
TBD < 85°C
TBD < 40°C
Operating
(I
CC2
, Max.)
TBD
K1B3216B8E-I
Mode 1
Mode 2
Mode 3
Industrial(-40~85°C)
1.7~1.95V
104MHz
1) Mode 1: Asynchronous read/ Asynchronous write
Mode 2: Synchronous burst read/ Asynchronous write
Mode 3: Synchronous burst read/ Synchronous burst write
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Revision 0.1
January 2007
K1B3216B8E
PIN DESCRIPTIONS & FUNCTION BLOCK DIAGRAM
1
2
3
4
5
6
Clk gen.
Preliminary
UtRAM
Pre-charge circuit
V
CC
V
CCQ
V
SS
V
SSQ
A
LB
OE
RFU
RFU
RFU
PS
B
A/DQ8
UB
RFU
RFU
CS
A/DQ0
Row
Addresses
Row
select
Memory
Array
C
A/DQ9
A/DQ10
RFU
RFU
A/DQ1
A/DQ2
D
VssQ
A/DQ11
A17
RFU
A/DQ3
Vcc
A/DQ
0
~A/DQ
7
Data
cont
Data
cont
Data
cont
I/O Circuit
E
F
Column Select
VccQ
A/DQ12
RFU
A16
A/DQ4
Vss
A/DQ
8
~A/DQ
15
A/DQ14 A/DQ13
RFU
RFU
A/DQ5
A/DQ6
Column Address
G
A/DQ15
A19
RFU
RFU
WE
A/DQ7
H
J
A18
RFU
RFU
RFU
RFU
A20
CLK
CS
ADV
OE
WE
UB
LB
PS
WAIT
CLK
ADV
RFU
RFU
RFU
Control Logic
54-FBGA - 6.00 x 8.00
Top View (Ball Down)
WAIT
TERMINOLOGY DESCRIPTION
Name
CLK
ADV
PS
CS
OE
WE
LB
UB
A16~A20
A/DQ0~A/DQ15
V
CC
V
CCQ
V
SS
V
SSQ
WAIT
Function
Clock
Address Valid
Mode Register set
Chip Select
Output Enable
Write Enable
Lower Byte (I/O
0
~
7
)
Upper Byte (I/O
8
~
15
)
Address 16 ~ Address 20
Address and Data
Inputs / Outputs
Voltage Source
I/O Voltage Source
Ground Source
I/O Ground Source
Valid Data Indicator
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input/Output
Power
Power
GND
GND
Output
Description
Synchronizes the memory to the system operating frequency during synchronous
operations. Commands are referenced to CLK.
Indicates that a valid address is present on the address inputs. Addresses can be
latched on the rising edge of ADV during asynchronous READ and WRITE oper-
ations.
PS low enables either PAR or DPD to be set.
CS low enables the chip to be active
CS high disables the chip and puts it into standby mode or deep power down
mode.
Enables the output buffers when LOW. when OE is HIGH, the output buffers are
disabled.
WE low enables the chip to start writing the data
UB ( LB) low enables upper byte (lower byte) to allow data Input/output from I/O
buffers.
Inputs for addresses during READ and WRITE operations. Addresses are inter-
nally latched during READ and WRITE cycles.
Address and Data I/Os: These pins are multiplexed address/ data bus.
Device Power supply. Power supply for device core operation.
I/O Power supply. Power supply for input/output buffers.
Ground for device core operation
Ground for input/output buffers
The WAIT signal is output signal indicating the status of the data on the bus
whether or not it is valid. WAIT is asserted when a burst crosses a word-line
boundary. WAIT is asserted and should be ignored during asynchronous and
page mode operations.
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Revision 0.1
January 2007
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