External Components
Component
R
CE
Function
Reference voltage for V
CE
-monitoring
10
⋅
R
CE
(
kΩ
)
-
V
CEstat
(
V
)
= ----------------------------------- – 1,4
10 + R
CE
(
kΩ
)
with R
VCE
= 1kΩ (1700V IGBT):
10
⋅
R
CE
(
kΩ
)
-
V
CEstat
(
V
)
= ----------------------------------- – 1,8
10 + R
CE
(
kΩ
)
(1)
Recommended Value
10kΩ < R
CE
< 100kΩ
18kΩ for SKM XX 123 (1200V)
36kΩ for SKM XX 173 (1700V)
(1.1)
C
CE
< 2,7nF
(2)
0,33nF for SKM XX 123 (1200V)
0,47nF for SKM XX 173 (1700V)
0,5μs < t
min
< 10μs
(3)
C
CE
Inhibit time for V
CE
- monitoring
15 – V
CEstat
(
V
)
-
t
min
=
τ
CE
⋅
ln ---------------------------------------
10 – V
CEstat
(
V
)
10
⋅
R
CE
(
kΩ
)
-
τ
CE
( μs )
= C
CE
(
nF
) ⋅
-----------------------------------
10 + R
CE
(
kΩ
)
R
VCE
R
ERROR
Collector series resistance for 1700V
IGBT-operation
Pull-up resistance at error output
U
Pull – Up
-----------------------
<
15mA
R
ERROR
1kΩ / 0,4W
1kΩ < R
ERROR
< 10kΩ
R
GON
R
GOFF
4)
5)
Turn-on speed of the IGBT
4)
Turn-off speed of the IGBT
5)
R
GON
> 3Ω
R
GOFF
> 3Ω
Higher resistance reduces free-wheeling diode peak recovery current, increases IGBT turn-on time.
Higher resistance reduces turn-off peak voltage, increases turn-off time and turn-off power dissipation
© by SEMIKRON 30-09-2008
Driver Electronic – PCB Drivers
2
PIN array
Fig. 2 shows the pin arrays. The input side (primary side) comprises 10 inputs (SKHI 22A / 21A 8 inputs), forming the
interface to the control circuit (see fig.1).
The output side (secondary side) of the hybrid driver shows two symmetrical groups of pins with 4 outputs, each forming
the interface to the power module. All pins are designed for a grid of 2,54 mm.
Primary side PIN array
PIN No. Designation
P14
P13
P12
P11
P10
P9
GND / 0V
V
S
V
IN1
free
/ERROR
TDT2
Explanation
related earth connection for input signals
+ 15V
±
4% voltage supply
switching signal input 1 (TOP switch)
positive 5V logic (for SKHI22A /21A, 15V logic)
not wired
error output, low = error; open collector output; max 30V / 15mA
(for SKHI22A /21A, internal 10kΩ pull-up resistor versus V
S
)
signal input for digital adjustment of interlocking time;
SKHI22B: to be switched by bridge to GND (see fig. 3)
SKHI22A /21A: to be switched by bridge to V
S
switching signal input 2 (BOTTOM switch);
positive 5V logic (for SKHI22A /21A, 15V logic)
related earth connection for input signals
signal input for neutralizing locking function;
to be switched by bridge to GND
signal input for digital adjustment of locking time;
to be switched by bridge to GND
P8
P7
P6
P5
V
IN2
GND / 0V
SELECT
TDT1
ATTENTION:
Inputs P6 and P5 are not existing for SKHI 22A/ 21A. The contactor tracks of the digital input signals P5/
P6/ P9 must not be longer than 20 mm to avoid interferences, if no bridges are connected.
Secondary side PIN array
PIN No. Designation Explanation
S20
S15
S14
S13
S12
S1
S6
S7
S8
S9
V
CE1
C
CE1
G
ON1
G
OFF1
E1
V
CE2
C
CE2
G
ON2
G
OFF2
E2
collector output IGBT 1 (TOP switch)
reference voltage adjustment with R
CE
and C
CE
gate 1 R
ON
output
gate 1 R
OFF
output
emitter output IGBT 1 (TOP switch)
collector output IGBT 2 (BOTTOM switch)
reference voltage adjustment with R
CE
and C
CE
gate 2 R
ON
output
gate 2 R
OFF
output
emitter output IGBT 2 (BOTTOM switch)
ATTENTION:
The connector leads to the power module should be as short as possible.
3
Driver Electronic – PCB Drivers
30-09-2008
© by SEMIKRON
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