PCS3P623Z05A,
PCS3P623Z05B,
PCS3P623Z09A,
PCS3P623Z09B
Product Preview
TIMING SAFEt Peak EMI
Reduction IC
Description
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PCS3P623Z05/09 is a versatile, 3.3 V Zero−delay buffer designed
to distribute Timing−Safe clocks with Peak EMI reduction.
PCS3P623Z05 is an eight−pin version, accepts one reference input
and drives out five low−skew Timing−Safe clocks. PCS3P623Z09
accepts one reference input and drives out nine low−skew
Timing−Safe clocks.
PCS3P623Z05/09 has a DLY_CTRL for adjusting the Input−Output
clock delay, depending upon the value of capacitor connected at this
pin to GND.
PCS3P623Z05/09 operates from a 3.3 V supply and is available in
two different packages, as shown in the ordering information table,
over commercial and Industrial temperature range.
Application
TSSOP−8
T SUFFIX
CASE 948AL
SOIC−8
S SUFFIX
CASE 751BD
TSSOP−16
T SUFFIX
CASE 948AN
SOIC−16
S SUFFIX
CASE 751BG
PCS3P623Z05/09 is targeted for use in Displays and memory
interface systems.
Features
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
•
Clock Distribution with Timing−Safe Peak EMI Reduction
•
Input Frequency Range: 20 MHz
−
50 MHz
•
Multiple Low Skew Timing−Safe Outputs:
•
•
•
•
•
•
PCS3P623Z05: 5 Outputs
PCS3P623Z09: 9 Outputs
External Input−Output Delay Control Option
Supply Voltage: 3.3 V
±
0.3 V
Commercial and Industrial Temperature Range
Packaging Information:
ASM3P623Z05: 8 pin SOIC, and TSSOP
ASM3P623Z09: 16 pin SOIC, and TSSOP
True Drop−in Solution for Zero Delay Buffer, ASM5P2305A / 09A
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
©
Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. P2
1
Publication Order Number:
PCS3P623Z05/D
PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B
PLL
CLKIN
PLL
CLKIN
CLKOUT1
PCS3P623Z05A/B
CLKOUT2
CLKOUT3
CLKOUT4
S2
S1
Select
Input
Decoding
DLY_CTRL
MUX
DLY_CTRL
CLKOUTA1
PCS3P623Z09A/B
CLKOUTA2
CLKOUTA3
CLKOUTA4
CLKOUTB1
CLKOUTB2
CLKOUTB3
CLKOUTB4
Figure 1. General Block Diagrams
Spread Spectrum Frequency Generation
Zero Delay and Skew Control
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the edge
rates also get faster. Analysis shows that a square wave is
composed of fundamental frequency and harmonics. The
fundamental frequency and harmonics generate the energy
peaks that become the source of EMI. Regulatory agencies
test electronic equipment by measuring the amount of peak
energy radiated from the equipment. In fact, the peak level
allowed decreases as the frequency increases. The standard
methods of reducing EMI are to use shielding, filtering,
multi−layer PCBs, etc. These methods are expensive.
Spread spectrum clocking reduces the peak energy by
reducing the Q factor of the clock. This is done by slowly
modulating the clock frequency. The PCS3P623Z05/09 uses
the center modulation spread spectrum technique in which
the modulated output frequency varies above and below the
reference frequency with a specified modulation rate. With
center modulation, the average frequency is the same as the
unmodulated frequency and there is no performance
degradation.
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the DLY_CTRL pin
is the internal feedback to the PLL, its relative loading can
adjust the input−output delay.
For applications requiring zero input−output delay, all
outputs, including DLY_CTRL, must be equally loaded.
Even if DLY_CTRL is not used, it must have a capacitive
load equal to that on other outputs, for obtaining zero
input−output delay.
Timing−Safe Technology
Timing−Safe technology is the ability to modulate a clock
source with Spread Spectrum technology and maintain
synchronization with any associated data path.
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2
PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B
Pin Configuration for PCS3P623Z05A/B
CLKIN
CLKOUT1
CLKOUT2
GND
1
2
PCS3P623Z05A/B
3
4
8
7
6
5
DLY_CTRL
CLKOUT4
VDD
CLKOUT3
Table 1. PIN DESCRIPTION FOR PCS3P623Z05A/B
Pin #
1
2
3
4
5
6
7
8
1.
2.
3.
4.
Pin Name
CLKIN (Note 1)
CLKOUT1 (Note 2)
CLKOUT2 (Note 2)
GND
CLKOUT3 (Note 2)
VDD
CLKOUT4 (Note 2)
DLY_CTRL
Type
I
O
O
P
O
P
O
O
Description
External reference Clock input, 5 V tolerant input
Buffered clock output (Note 4)
Buffered clock output (Note 4)
Ground
Buffered clock output (Note 4)
3.3 V supply
Buffered clock output (Note 4)
External Input−Output Delay control. This pin can be used as clock output (Note 4)
Weak pull down
Weak pull−down on all outputs
Weak pull−up on these Inputs
Buffered clock output is Timing−Safe
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3
PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B
Pin Configuration for PCS3P623Z09A/B
CLKIN
CLKOUTA1
CLKOUTA2
VDD
GND
CLKOUTB1
CLKOUTB2
S2
1
2
3
4
5
6
7
8
PCS3P623Z09A/B
16
15
14
13
12
11
10
9
DLY_CTRL
CLKOUTA4
CLKOUTA3
VDD
GND
CLKOUTB4
CLKOUTB3
S1
Table 2. PIN DESCRIPTION FOR PCS3P623Z09A/B
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
5.
6.
7.
8.
Pin Name
CLKIN (Note 5)
CLKOUTA1 (Note 6)
CLKOUTA2 (Note 6)
VDD
GND
CLKOUTB1 (Note 6)
CLKOUTB2 (Note 6)
S2 (Note 7)
S1 (Note 7)
CLKOUTB3 (Note 6)
CLKOUTB4 (Note 6)
GND
VDD
CLKOUTA3 (Note 6)
CLKOUTA4 (Note 6)
DLY_CTRL (Note 6)
Pin Type
I
O
O
P
P
O
O
I
I
O
O
P
P
O
O
O
Description
External reference Clock input, 5 V tolerant input
Buffered clock Bank A output (Note 8)
Buffered clock Bank A output (Note 8)
3.3 V supply
Ground
Buffered clock Bank B output (Note 8)
Buffered clock Bank B output (Note 8)
Select input, bit 2. See
Select Input Decoding table for PCS3P623Z09
for more details
Select input, bit 1. See
Select Input Decoding table for PCS3P623Z09
for more details
Buffered clock Bank B output (Note 8)
Buffered clock Bank B output (Note 8)
Ground
3.3 V supply
Buffered clock Bank A output (Note 8)
Buffered clock Bank A output (Note 8)
External Input−Output Delay control. This pin can be used as clock output.
Weak pull down
Weak pull−down on all outputs
Weak pull−up on these Inputs
Buffered clock output is Timing−Safe
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4
PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B
Table 3. SELECT INPUT DECODING TABLE FOR PCS3P623Z09
S2
0
0
1
1
S1
0
1
0
1
CLKOUT A1
−
A4
Three−state
Driven
Driven
Driven
CLKOUT B1
−
B4
Three−state
Three−state
Driven
Driven
DLY_CTRL
(Note 9)
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shut−Down
N
N
Y
N
9. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the
reference and the Output.
Table 4. SPREAD SPECTRUM CONTROL AND INPUT−OUTPUT SKEW TABLE
Frequency (MHz)
32
Device
PCS3P623Z05A / 09A
PCS3P623Z05B / 09B
10. T
SKEW
is measured in units of the Clock Period.
Deviation (+
%)
0.125
0.25
Input−Output Skew (+T
SKEW
)
(Note 10)
0.125
0.25
Table 5. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VIN
T
STG
T
s
T
J
T
DV
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (CLKIN)
Storage temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Rating
−0.5
to +4.6
−0.5
to +7
−65
to +125
260
150
2
°C
°C
°C
KV
Unit
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 6. OPERATING CONDITIONS
Parameter
VDD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Description
Min
3.0
−40
Max
3.6
+85
30
7
Unit
V
°C
pF
pF
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