STK20C04
STK20C04
CMOS nvSRAM
High Performance
512 x 8 Nonvolatile Static RAM
FEATURES
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30, 35 and 45ns Access Times
15, 20 and 25ns Output Enable Access
Unlimited Read and Write to
SRAM
Hardware
STORE
Initiation
Automatic
STORE
Timing
10
5
STORE
cycles to
EEPROM
10 year data retention in
EEPROM
Automatic
RECALL
on Power Up
Hardware
RECALL
Initiation
Unlimited
RECALL
cycles from
EEPROM
Single 5V±10% Operation
Commercial and Industrial Temperatures
Available in 600 mil PDIP package
DESCRIPTION
The Simtek STK20C04 is a fast static
RAM
(30, 35,
45ns), with a nonvolatile electrically-erasable
PROM
(
EEPROM
) element incorporated in each static memory
cell. The
SRAM
can be read and written an unlimited
number of times, while independent nonvolatile data
resides in
EEPROM
. Data may easily be transferred
from the
SRAM
to the
EEPROM
(
STORE
), or from the
EEPROM
to the
SRAM
(
RECALL
) using the NE pin. It
combines the high performance and ease of use of a
fast
SRAM
with nonvolatile data integrity.
The STK20C04 features the industry standard pinout
for nonvolatile
RAM
s in a 28-pin 600 mil plastic DIP.
LOGIC BLOCK DIAGRAM
EEPROM ARRAY
64 X 64
STORE
ROW DECODER
PIN CONFIGURATIONS
NE
NC
A
7
A
6
5
4
3
2
1
0
0
1
2
14
15
6
7
8
9
10
11
12
13
23
22
21
20
19
18
17
16
1
2
3
4
5
28
27
26
25
24
V
CC
W
NC
A
8
A
3
A
4
A
5
A
6
A
7
A
8
STATIC RAM
ARRAY
64 X 64
RECALL
A
A
A
A
A
A
DQ
DQ
DO
NC
NC
G
NC
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
V
SS
28 - 600 PDIP
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
E
W
INPUT BUFFERS
COLUMN I/O
STORE/
RECALL
CONTROL
COLUMN DECODER
PIN NAMES
A
0
- A
8
W
DQ
0
- DQ
7
G
NE
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Nonvolatile Enable
Power (+5V)
Ground
A
0
A
1
A
2
E
G
NE
V
CC
V
SS
2-39
STK20C04
ABSOLUTE MAXIMUM RATINGS
a
Voltage on typical input relative to V
SS
. . . . . . . . . . . . . –0.6V to 7.0V
Voltage on DQ
0-7
and G. . . . . . . . . . . . . . . . . . .–0.5V to (V
CC
+0.5V)
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
(One output at a time, one second duration)
Note a:
Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
I
CC b
1
(V
CC
= 5.0V
±
10%)
INDUSTRIAL
MIN
MAX
85
80
75
50
30
27
23
1
±1
±5
2.2
V
SS
–.5
2.4
0.4
0
70
–40
0.4
85
V
CC
+.5
0.8
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
V
°C
t
AVAV
= 30ns
t
AVAV
= 35ns
t
AVAV
= 45ns
All inputs at
V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
27
23
20
t
AVAV
= 30ns
t
AVAV
= 35ns
t
AVAV
= 45ns
E
≥
V
IH
; all others cycling
E
≥
(V
CC
– 0.2V)
all others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
±1
±5
2.2
V
SS
–.5
2.4
V
CC
+.5
0.8
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
All Inputs
All Inputs
I
OUT
= –4mA
I
OUT
= 8mA
NOTES
MIN
MAX
80
75
65
PARAMETER
Average V
CC
Current
I
CC
I
SB
d
2
c
1
Average V
CC
Current
during
STORE
cycle
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
50
I
SB
c
2
Average V
CC
Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current (Any Input)
Off State Output Leakage Current
Input Logic "1" Voltage
Input Logic "0" Voltage
Output Logic "1" Voltage
Output Logic "0" Voltage
Operating Temperature
1
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
Note b: I
CC1
is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: Bringing E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note d: I
CC 2
is the average current required for the duration of the store cycle (t
STORE
) after the sequence (t
WC
) that initiates the cycle.
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . .
≤
5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
Output
5.0V
480 Ohms
CAPACITANCE
SYMBOL
C
IN
C
OUT
(T
A
=25°C, f=1.0MHz)
e
255 Ohms
PARAMETER
Input Capacitance
Output Capacitance & W
MAX
7
7
UNITS
pF
pF
CONDITIONS
∆V
= 0 to 3V
∆V
= 0 to 3V
30pF
INCLUDING
SCOPE
AND FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
2-40
STK20C04
READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
11A
Note c:
Note e:
Note f:
Note g:
#1, #2
t
ELQV
t
AVAVRg
t
AVQVh
t
GLQV
t
AXQX
t
ELQX
t
EHQZi
t
GLQX
t
GHQZi
t
ELICCHe
t
EHICCLc,e
t
WHQV
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
t
WR
PARAMETER
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Write Recovery Time
0
25
35
0
18
0
25
45
5
5
18
0
20
0
25
55
30
30
15
5
5
20
0
25
STK20C04-30
MIN
MAX
30
35
35
20
5
5
25
STK20C04-35
MIN
MAX
35
45
45
25
(V
CC
= 5.0V
±
10%)
STK20C04-45
MIN
MAX
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bringing E high will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Parameter guaranteed but not tested.
NE must be high during entire cycle.
For READ CYCLE #1 and #2, W and NE must be high for entire cycle.
Note h: Device is continuously selected with E low and G low.
Note i: Measured
±
200mV from steady state output voltage.
READ CYCLE #1
f,g,h
2
t
AVAVR
ADDRESS
5
t
AXQX
DQ (Data Out)
3
t
AVQV
DATA VALID
W
11A
t
WHQV
READ CYCLE #2
f,g
2
t
AVAVR
ADDRESS
1
t
ELQV
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ
DATA VALID
E
t
ELQX
4
6
G
t
GLQV
8
t
GLQX
DQ (Data Out)
10
t
ELICCH
I
CC
ACTIVE
STANDBY
W
11A
t
WHQV
2-41
STK20C04
WRITE CYCLES #1 & #2
SYMBOLS
NO.
12
13
14
15
16
17
18
19
20
21
Note f:
#1
t
AVAVW
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZi,m
t
WHQX
#2
t
AVAVW
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
#3
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
PARAMETER
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold After End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
5
STK20C04-30
MIN
45
35
35
30
0
35
0
0
35
5
MAX
STK20C04-35
MIN
45
35
35
30
0
35
0
0
35
5
MAX
(V
CC
= 5.0V
±
10%)
STK20C04-45
MIN
45
35
35
30
0
35
0
0
35
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NE must be high during entire cycle.
Note i: Measured
±
200mV from steady state output voltage.
Note k: E or W must be high during address transitions.
Note m: If W is low when E goes low, the outputs remain in the high impedance state.
WRITE CYCLE #1:
W CONTROLLED
f,k
12
t
AVAVW
ADDRESS
14
t
ELWH
E
18
17
t
AVWH
19
t
WHAX
t
AVWL
W
13
t
WLWH
15
t
DVWH
16
t
WHDX
DATA IN
20
t
WLQZ
DATA OUT
PREVIOUS DATA
DATA VALID
21
t
WHQX
HIGH IMPEDANCE
WRITE CYCLE #2:
E CONTROLLED
f,k
12
t
AVAVW
ADDRESS
18
t
AVEL
E
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
DATA IN
DATA VALID
14
t
ELEH
19
t
EHAX
16
t
EHDX
DATA OUT
HIGH IMPEDANCE
2-42
STK20C04
NONVOLATILE MEMORY OPERATION
MODE SELECTION
E
H
L
L
L
L
L
L
W
X
H
L
H
L
L
H
G
X
L
X
L
H
L
H
NE
X
H
H
L
L
L
X
MODE
Not Selected
Read RAM
Write RAM
Nonvolatile
RECALL
n
Nonvolatile
STORE
No operation
POWER
Standby
Active
Active
Active
I
CC
2
Active
STORE CYCLES #1 & #2
SYMBOLS
NO.
22
23
24
25
26
27
28
t
NLWL
t
ELWL
t
WLEL
#1
t
WLQXp
t
WLNHq
t
GHNL
t
GHEL
t
NLEL
#2
t
ELQXS
t
ELNHS
Alt.
t
STORE
t
WC
PARAMETER
(V
CC
= 5.0V
±
10%)
MIN
MAX
10
45
0
0
0
0
0
UNITS
ms
ns
ns
ns
ns
ns
ns
STORE
Cycle Time
STORE
Initiation Cycle Time
Output Disable Set-up to NE Fall
Output Disable Set-up to E Fall
NE Set-up
Chip Enable Set-up
Write Enable Set-up
Note: n: An automatic
RECALL
also takes place at power up, starting when V
CC
exceeds 3.8V, and taking t
RECALL
from the time at which V
CC
exceeds 4.5V.
V
CC
must not drop below 3.8V once it has exceeded it for the
RECALL
to function properly.
Note o: If E is low for any period of time in which W is high while G and NE are low, then a
RECALL
cycle may be initiated.
Note p: Measured with W and NE both returned high, and G returned low. Note that
STORE
cycles are inhibited/aborted by V
CC
< 3.8V (STORE inhibit).
Note q: Once t
WC
has been satisfied by NE, G, W and E, the
STORE
cycle is completed automatically. Any of NE, G, W or E may be used to terminate the
STORE
initiation cycle.
STORE CYCLE #1:
W CONTROLLED
o
NE
G
W
24
t
GHNL
27
t
ELWL
26
t
NLWL
23
t
WLNH
E
DQ (Data Out)
HIGH IMPEDANCE
22
t
WLQX
STORE CYCLE #2:
E CONTROLLED
o
NE
25
t
GHEL
G
W
E
28
t
WLEL
23
t
ELNHS
22
t
ELQXS
26
t
NLEL
DQ (Data Out)
HIGH IMPEDANCE
2-43
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