TSPC603R
PowerPC 603e™ RISC MICROPROCESSOR Family
PID7t-603e Specification
DESCRIPTION
The PID7t-603e implementation of PowerPC603e (after
named 603r) is a low-power implementation of reduced
instruction set computer (RISC) microprocessors PowerPC™
family. The 603r implements 32-bit effective addresses, inte-
ger data types of 8, 16 and 32 bits, and floating-point data types
of 32 and 64 bits.
The 603r is a low-power 2.5/3.3-volt design and provides four
software controllable power-saving modes.
The 603r is a superscalar processor capable of issuing and
retiring as many as three instructions per clock. Instructions
can execute out of order for increased performance ; however,
the 603r makes completion appear sequential. The 603r inte-
grates five execution units and is able to execute five instruc-
tions in parallel.
The 603r provides independent on-chip, 16-Kbyte, four-way
set-associative, physically addressed caches for instructions
and data and on-chip instruction and data memory manage-
ment units (MMUs). The MMUs contain 64-entry, two-way set-
associative, data and instruction translation lookaside buffers
that provide support for demand-paged virtual memory
address translation and variable-sized block translation.
The 603r has a selectable 32 or 64-bit data bus and a 32-bit
address bus. The 603r interface protocol allows multiple mas-
ters to complete for system resources through a central exter-
nal arbiter. The 603r supports single-beat and burst data trans-
fers for memory accesses, and supports memory-mapped I/O.
The 603r uses an advanced, 2.5/3.3-V CMOS process techno-
logy and maintains full interface compatibility with TTL devi-
ces.
The 603r integrates in system testability and debugging fea-
tures through JTAG boundary-scan capability.
G suffix
CBGA 255
Ceramic Ball Grid Array
GS suffix
CI–CGA 255
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
MAIN FEATURES
H
7.4 SPECint95, 6.1 SPECfp95 @ 300 MHz (estimated)
H
Superscalar (3 instructions per clock peak).
H
Dual 16KB caches.
H
Selectable bus clock.
H
32-bit compatibility PowerPC implementation.
H
On chip debug support.
H
P
D
typical = 3.5 Watts (266 MHz), full operating conditions.
H
Nap, doze and sleep modes for power savings.
H
Branch folding.
H
64-bit data bus (32-bit data bus option).
H
4-Gbyte direct addressing range.
H
Pipelined single/double precision float unit.
H
H
H
H
IEEE 754 compatible FPU.
IEEE P 1149-1 test mode (JTAG/C0P).
f
int
max = 300 MHz.
f
bus
max = 75 MHz.
Compatible CMOS input / TTL Output.
SCREENING / QUALITY / PACKAGING
This product is manufactured in full compliance with:
H
CI–CGA 255 : MIL-STD-883 class Q or According to TCS
H
H
H
H
standards (planned)
CBGA 255 : Upscreenings based upon TCS standards
Full military temperature range (T
c
= -55°C, T
c
= +125°C)
Industrial temperature range (T
c
= -40°C, T
c
= +110°C)
Internal // I/O Power Supply = 2.5
±
5 % // 3.3 V
±
5 %.
255 pin CBGA package and 255 pin CBGA with SCI (CI–
CGA) package.
January 1999
1/38
TSPC603R
SUMMARY
A. GENERAL DESCRIPTION . . . . . . . . . . . . . . 3
1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1. CBGA package . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2. Pinout listing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 7
5.1.3.
5.1.4.
5.1.5.
5.1.6.
5.1.7.
Condition Register (CR) . . . . . . . . . . . . 22
Floating-Point Status and Control Register
(FPSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Machine State Register (MSR) . . . . . . 22
Segment Registers (SRs) . . . . . . . . . . . 22
Special-Purpose Registers (SPRs) . . . 22
5.2. Instruction set and addressing modes . . . . 25
5.2.1.
5.2.2.
PowerPC instruction set and addressing
modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PowerPC 603r microprocessor instruction
set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
B. DETAILED SPECIFICATIONS . . . . . . . . . . 10
1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . 10
3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2. Design and construction . . . . . . . . . . . . . . . . 10
3.2.1.
3.2.2.
Terminal connections . . . . . . . . . . . . . . . 10
Lead material and finish . . . . . . . . . . . . 10
5.3. Cache implementation . . . . . . . . . . . . . . . . . . 26
5.3.1.
5.3.2.
PowerPC cache characteristics . . . . . . 26
PowerPC 603r microprocessor cache
implementation . . . . . . . . . . . . . . . . . . . . 26
5.4. Exception model . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.1.
5.4.2.
PowerPC exception model . . . . . . . . . . 27
PowerPC 603r microprocessor exception
model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5. Memory management . . . . . . . . . . . . . . . . . . 31
5.5.1.
5.5.2.
PowerPC memory management . . . . . 31
PowerPC 603r microprocessor memory
management . . . . . . . . . . . . . . . . . . . . . . 31
3.3. Absolute maximum ratings . . . . . . . . . . . . . . 10
3.4. Recommended operating conditions . . . . . . 11
3.5. Thermal characteristics . . . . . . . . . . . . . . . . . 11
3.6. Power consideration . . . . . . . . . . . . . . . . . . . 12
3.6.1.
3.6.2.
3.6.3.
3.6.4.
3.6.5.
Dynamic Power Management . . . . . . .
Programmable Power Modes . . . . . . . .
Power Management Modes . . . . . . . . .
Power Management Software
Considerations . . . . . . . . . . . . . . . . . . . .
Power dissipation . . . . . . . . . . . . . . . . . .
12
12
12
14
14
5.6. Instruction timing . . . . . . . . . . . . . . . . . . . . . . 31
6. PREPARATION FOR DELIVERY . . . . . . . . . . . . . 32
6.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2. Certificate of compliance . . . . . . . . . . . . . . . . 32
7. HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8. PACKAGES MECHANICAL DATA . . . . . . . . . . . 33
8.1.CBGA package parameters . . . . . . . . . . . . . . 33
3.7. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . 15
4.1. General requirements . . . . . . . . . . . . . . . . . . 15
4.2. Static characteristics . . . . . . . . . . . . . . . . . . . 15
4.3. Dynamic characteristics . . . . . . . . . . . . . . . . 16
4.3.1.
4.3.2.
4.3.3.
Clock AC specifications . . . . . . . . . . . . . 16
Input AC specifications . . . . . . . . . . . . . 17
Output AC specifications . . . . . . . . . . . . 18
8.2. Mechanical dimensions of the CBGA
package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.3. CI–CGA package parameters . . . . . . . . . . . 34
8.4. Mechanical dimensions of the CI–CGA
package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9. CLOCK RELATIONSHIPS CHOICE . . . . . . . . . . 35
10. SYSTEM DESIGN INFORMATION . . . . . . . . . . . 36
10.1 PLL Power Supply Filtering
. . . . . . . . . . . . .
36
10.2 Decoupling Recommendations
. . . . . . . . . .
36
10.3 Connection Recommendations
. . . . . . . . . .
36
10.4 Pull–up Resistor Requirements
. . . . . . . . .
37
11. ORDERING INFORMATION . . . . . . . . . . . . . . . . 38
4.4. JTAG AC timing specifications . . . . . . . . . . . 20
5. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . 22
5.1. PowerPC registers and programming
model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.1.
5.1.2.
General-Purpose Registers (GPRs) . . 22
Floating-Point Registers (FPRs) . . . . . 22
2/38
TSPC603R
A. GENERAL DESCRIPTION
Fetch
Unit
Completion
Unit
Dispatch
Unit
Branch
Unit
Integer
Unit
Gen
Reg
Unit
Gen
Re-
name
Load/
Store
Unit
FP
Re-
name
FP
Reg
File
Float
Unit
D MMU
16K Data Cache
I MMU
16K Inst. Cache
Bus Interface Unit
32b
address
64b
data
System Bus
Figure 1 :
Block diagram
1. INTRODUCTION
The 603r is a low-power implementation of the PowerPC microprocessor family of reduced instruction set commuter (RISC) micro-
processors. The 603r implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer
data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC
architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.
The 603r provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep modes) are static in
nature, and progressively reduce the amount of power dissipated by the processor. The fourth is a dynamic power management
mode that causes the functional units in the 603r to automatically enter a low-power mode when the functional units are idle without
affecting operational performance, software execution, or any external hardware.
The 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute
out of order for increased performance ; however, the 603r makes completion appear sequential.
The 603 e integrates five execution units - an integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store
unit (LSU) and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with
rapid execution times yield high efficiency and throughput for 603r-based systems. Most integer instructions execute in one clock
cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every clock cycle.
The 603r provides independent on-chip, 16 Kbyte, four-way set-associative, physically addressed caches for instructions and data
and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data
and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address
translation and variable-sized block translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The
603r also supports block address translation through the use of two independent instruction and data block address translation (IBAT
and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during
block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT
translation takes priority.
The 603r has a selectable 32 - or 64-bit - data bus and a 32-bit address bus. The 603r interface protocol allows multiple masters to
compete for system resources through a central external arbiter. The 603r provides a three-state coherency protocol that supports
the exclusive, modified, and invalid cache states. This protocol as a compatible subset of the MESI (modified/exclusive/shared/in-
valid) four-state protocol and operates coherently in systems that contain four-state caches. The 603r supports single-beat and burst
data transfers for memory accesses, and supports memory-mapped I/O.
The 603r uses an advanced, 0.29
mm
5 metal layer CMOS process technology and maintains full interface compatibility with TTL
devices.
3/38
TSPC603R
2. PIN ASSIGNMENTS
2.1. CBGA 255 and CI–CGA 255 packages
Figure 2 (pin matrix) shows the pinout as viewed from the top of the CBGA and CI–CGA packages. The direction of the top surface
view is shown by the side profile of the packages.
Pin matrix top view
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Substrate Assembly
Die
View
CBGA 255
Encapsulant
CI–CGA 255
Not to scale
Figure 2 :
CBGA 255 and CI–CGA 255 Top view
4/38
TSPC603R
2.2. Pinout listing
Table 1 : Power and ground pins
VDD
2
PLL (AVDD)
Internal logic
Output drivers
A10
F06, F08, F09, F11, G07, G10, H06, H08, H09, H11,
J06, J08, J09, J11, K07, K10, L06, L08, L09, L11
C07, E05, E07, E10, E12, G03, G05, G12, G14,
K03, K05, K12, K14, M05, M07, M10, M12, P07, P10
C05, C12, E03, E06, E08, E09, E11, E14, F05, F07,
F10, F12, G06, G08, G09, G11, H05, H07, H10,
H12 J05 J07 J10 J12 K06 K08 K09 K11 L05
H12, J05, J07, J10, J12, K06, K08, K09, K11, L05,
L07, L10, L12, M03, M06, M08, M09, M11, M14,
P05, P12
GND
Table 2 : Signal pinout listing
Signal name
A[0–31]
CBGA Pin number
C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, G02, E15, H01, E16,
H02, F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15,
P01
L02
K04
C01, B04, B03, B02
A04
J04
L01
B06
E01
D08
A06
D07
B01, B05
J14
N01
H15
G04
Active
High
I/O
I/O
AACK
ABB
AP[0–3]
APE
ARTRY
BG
BR
CI
CKSTP_IN
CKSTP_OUT
CLK_OUT
CSE[0-1]
DBB
DBG
DBDIS
DBWO
DH[0-31]
DL[0-31]
Low
Low
High
Low
Low
Low
Low
Low
Low
Low
-
High
Low
Low
Low
Low
Input
I/O
I/O
Output
I/O
Input
Output
Output
Input
Output
Output
Output
I/O
Input
Input
Input
I/O
I/O
P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P09, N09, T10, R09, High
T09, P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, T04
K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16,
P15, R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04,
T03, R04
M02, L03, N02, L04, R01, P02, M04, R02
A05
G16
F01
A07
B15
D11
High
DP[0-7]
DPE
DRTRY
GBL
HRESET
INT
L1_TSTCLK
1
High
Low
Low
Low
Low
Low
-
I/O
Output
Input
I/O
Input
Input
Input
5/38
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