Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state
FEATURES
•
Wide supply voltage range from 1.65 to 3.6 V
•
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
•
3.6 V tolerant inputs/outputs
•
CMOS low power consumption
•
Direct interface with TTL levels (2.7 to 3.6 V)
•
Power-down mode
•
Latch-up performance exceeds
≤250
mA
•
ESD protection:
2000 V Human Body Model (JESD22-A114-A)
200 V Machine Model (JESD22-A115-A).
DESCRIPTION
74ALVC574
The 74ALVC574 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74ALVC574 is an octal D-type flip-flop featuring
separate D-type inputs for each flip-flop and 3-state
outputs for bus oriented applications. A clock (CP) input
and an output enable (OE) input are common to all
flip-flops.
The eight flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is
available at the outputs. When OE is HIGH, the outputs go
to the high-impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
The ‘574’ is functionally identical to the ‘374’, but the ‘374’
has a different pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay CP to Q
n
CONDITIONS
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
C
I
C
PD
input capacitance
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes 1 and 2
outputs enabled
outputs disabled
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
21
13
pF
pF
TYPICAL
3.1
2.3
2.5
2.5
3.5
UNIT
ns
ns
ns
ns
pF
2002 Mar 04
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
PINS
74ALVC574D
74ALVC574PW
FUNCTION TABLE
See note 1.
INPUT
OPERATING MODES
OE
Load and read register
Latch and read register
L
L
H
H
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOWvoltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
↑
= LOW-to-HIGH clock transition;
Z = high-impedance OFF-state.
PINNING
PIN
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
12, 13, 14, 15, 16, 17, 18,
19
20
OE
Q
0
to Q
7
GND
CP
D
7
to D
0
V
CC
SYMBOL
CP
↑
↑
↑
↑
D
n
l
h
l
h
INTERNAL
FLIP-FLOPS
L
H
L
H
20
20
PACKAGE
SO
TSSOP
MATERIAL
plastic
plastic
74ALVC574
CODE
SOT163-1
SOT360-1
OUTPUT
Q
0
to Q
7
L
H
Z
Z
DESCRIPTION
output enable input (active LOW)
3-state flip-flop output
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
data input
supply voltage
2002 Mar 04
3
MCU
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