EEWORLDEEWORLDEEWORLD

Part Number

Search

531UB547M000DGR

Description
CMOS/TTL Output Clock Oscillator, 547MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531UB547M000DGR Overview

CMOS/TTL Output Clock Oscillator, 547MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531UB547M000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency547 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS/TTL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Ask about the serial port problem when kernel is cut
The newly made board has 3 serial ports, and serial port 1 is used as a debug port. Now I don't want to use serial port 1 as a debug output port, but use it as a general serial port. But there is a pr...
huangxu20051207 Embedded System
It’s finally Monday, looking forward to the group purchase content.
:titter: Group buying is about to start again, so nervous~~...
lcofjp TI Technology Forum
Allwinner heterogeneous multi-core AI intelligent vision V853 development board evaluation - separate compilation and testing of V853 SDK LVGL routines
# Separately compile and test the LVGL routines of V853 SDK. Recently, when I was studying the routines in the SDK, I accidentally discovered that the routines in the SDK can also be compiled separate...
IC爬虫 Domestic Chip Exchange
The evolution history of the world's famous car brand logo - Peugeot
Peugeot was founded in 1812 in Montbeliard, France, and was named after the family ancestor Jean-Jaques Peugeot (1699-1741). The brothers Jean-Pierre and Jean-Frederic converted their windmill into a ...
1ying Automotive Electronics
A question encountered during the written test, experts help to answer
Vcc=5V, VoH(min)=3.4V, VoL(max)=0.2V, ViH(min)=2.0V, ViL(max)=0.8V, IiH=0.04ma. What is the maximum value of R for the following NOT gate to correctly identify the signal sent by the previous stage?...
pxy94 MCU
#Micropython大战# Part 2: Publish an original mciropython tutorial to win gifts!
[size=5][color=#ff0000]#Micropython Battle#Activity initiation and purpose:[/color][/size] [size=4]Call on everyone to play Micropython, gather everyone's strength to explore the gameplay of Micropyth...
okhxyyo MicroPython Open Source section

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2221  2919  1388  789  1111  45  59  28  16  23 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号