256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8)
Many-Time Programmable Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
FEATURES:
• Organized as 32K x8 / 64K x8 / 128K x8 / 256K x8
• 5.0V (4.5-5.5V) Read Operation
• Superior Reliability
– Endurance: At least 1000 Cycles
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Read Access Time
– 70 and 90 ns
• Fast Byte-Program Operation
– Byte-Program Time: 20 µs (typical)
– Chip-Program Time:
0.7 seconds (typical) for SST27SF256
1.4 seconds (typical) for SST27SF512
2.8 seconds (typical) for SST27SF010
5.6 seconds (typical) for SST27SF020
PRODUCT DESCRIPTION
The SST27SF256/512/010/020 are a 32K x8 / 64K x8 /
128K x8 / 256K x8 CMOS, Many-Time Programmable
(MTP) low cost flash, manufactured with SST’s propri-
etary, high performance SuperFlash technology. The
split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared
with alternate approaches. These MTP devices can be
electrically erased and programmed at least 1000 times
using an external programmer with a 12 volt power
supply. They have to be erased prior to programming.
These devices conform to JEDEC standard pinouts for
byte-wide memories.
Featuring high performance Byte-Program, the
SST27SF256/512/010/020 provide a Byte-Program
time of 20 µs. Designed, manufactured, and tested for a
wide spectrum of applications, these devices are offered
with an endurance of at least 1000 cycles. Data retention
is rated at greater than 100 years.
The SST27SF256/512/010/020 are suited for applica-
tions that require infrequent writes and low power non-
volatile storage. These devices will improve flexibility,
efficiency, and performance while matching the low cost
in nonvolatile applications that currently use UV-
EPROMs, OTPs, and mask ROMs.
To meet surface mount and conventional through hole
requirements, the SST27SF256/512 are offered in 28-
pin PDIP, 32-pin PLCC and 32-pin TSOP packages. The
SST27SF010/020 are offered in 32-pin PDIP, 32-pin
PLCC and 32-pin TSOP packages. See Figures 1,2 and
3 for pinouts.
Device Operation
The SST27SF256/512/010/020 are a low cost flash
solution that can be used to replace existing UV-
EPROM, OTP, and mask ROM sockets. These devices
are functionally (read and program) and pin compatible
with industry standard EPROM products. In addition to
EPROM functionality, these devices also support electri-
cal erase operation via an external programmer. They do
not require a UV source to erase, and therefore the
packages do not have a window.
Read
The Read operation of the SST27SF256/512/010/020 is
controlled by CE# and OE#. Both CE# and OE# have to
be low for the system to obtain data from the outputs.
Once the address is stable, the address access time is
equal to the delay from CE# to output (T
CE
). Data is
available at the output after a delay of T
OE
from the falling
edge of OE#, assuming that CE# pin has been low and
the addresses have been stable for at least T
CE
- T
OE
.
• Electrical Erase Using Programmer
– Does Not Require UV Source
– Chip-Erase Time: 100 ms (typical)
• TTL I/O Compatibility
• JEDEC Standard Byte-wide EPROM Pinouts
• 12V Power Supply for Programming/Erase
• Packages Available
– 28-Pin PDIP for SST27SF256/512
– 32-Pin PDIP for SST27SF010/020
– 32-Pin PLCC
– 32-Pin TSOP (8mm x 14mm)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
© 2000 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon Storage Technology, Inc.
1
502-03 2/00
These specifications are subject to change without notice.
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
When the CE# pin is high, the chip is deselected and a
typical standby current of 10 µA is consumed. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when either
CE# or OE# is high.
Byte-Program Operation
The SST27SF256/512/010/020 are programmed by us-
ing an external programmer. The programming mode for
SST27SF256/010/020 is activated by asserting 12V
(±5%) on V
PP
pin, V
CC
= 5V (±5%), V
IL
on CE# pin, and
V
IH
on OE# pin. The programming mode for
SST27SF512 is activated by asserting 12V (±5%) on
OE#/V
PP
pin, V
CC
= 5V (±5%), and V
IL
on CE# pin. These
devices are programmed byte-by-byte with the desired
data at the desired address using a single pulse (CE# pin
low for SST27SF256/512 and PGM# pin low for
SST27SF010/020) of 20 µs. Using the MTP program-
ming algorithm, the Byte-Programming process contin-
ues byte-by-byte until the entire chip has been pro-
grammed.
Chip-Erase Operation
The only way to change a data from a “0” to “1” is by
electrical erase that changes every bit in the device to “1”.
Unlike traditional EPROMs, which use UV light to do the
Chip-Erase, the SST27SF256/512/010/020 uses an
electrical Chip-Erase operation. This saves a significant
amount of time (about 30 minutes for each Erase opera-
tion). The entire chip can be erased in a single pulse of
100 ms (CE# pin low for SST27SF256/512 and PGM#
pin for SST27SF010/020). In order to activate the Erase
mode for SST27SF256/010/020, the 12V (±5%) is ap-
plied to V
PP
and A
9
pins, V
CC
= 5V (±5%), V
IL
on CE# pin,
and V
IH
on OE# pin. In order to activate Erase mode for
SST27SF512, the 12V (±5%) is applied to OE#/V
PP
and
A
9
pins, V
CC
= 5V (±5%), and V
IL
on CE# pin. All other
address and data pins are “don’t care”. The falling edge
of CE# (PGM# for SST27SF010/020) will start the Chip-
Erase operation. Once the chip has been erased, all
bytes must be verified for FF. Refer to Figures 13, 14 and
15 for the flowcharts.
Product Identification Mode
The Product Identification mode identifies the devices as
the SST27SF256, SST27SF512, SST27SF010 and
SST27SF020 and manufacturer as SST. This mode may
be accessed by the hardware method. To activate this
mode for SST27SF256/010/020, the programming
equipment must force V
H
(12V±5%) on address A
9
with
V
PP
pin at V
CC
(5V±10%) or V
SS
. To activate this mode
for SST27SF512, the programming equipment must
force V
H
(12V±5%) on address A
9
with OE#/V
PP
pin at
V
IL
. Two identifier bytes may then be sequenced from the
device outputs by toggling address line A
0
. For details,
see Tables 3, 4 and 5 for hardware operation.
T
ABLE
1: P
RODUCT
I
DENTIFICATION
T
ABLE
Byte
Manufacturer’s Code
0000 H
Device Code:
SST27SF256
01 H
SST27SF512
01 H
SST27SF010
01 H
SST27SF020
01 H
Data
BF H
A3 H
A4 H
A5 H
A6 H
502 PGM T1.0
© 2000 Silicon Storage Technology, Inc.
2
502-03 2/00
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