S29AL016D
16 Mbit (2 M x 8-Bit/1 M x 16-Bit), 3 V
Boot Sector Flash
This product has been retired and is not recommended for designs. For new and current designs, S29AL016J supercedes
S29AL016D. This is the factory-recommended migration path. Please refer to the S29AL016J data sheet for specifications and
ordering information.
Distinctive Characteristics
Architectural Advantages
Single Power Supply Operation
– Full voltage range: 2.7 to 3.6 volt read and write operations for
battery-powered applications
Manufactured on 200 nm Process Technology
– Fully compatible with 200 nm Am29LV160D and MBM29LV160E
devices
Flexible Sector Architecture
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte
sectors (byte mode)
– One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32
Kword sectors (word mode)
Sector Protection Features
– A hardware method of locking a sector to prevent any program or
erase operations within that sector
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Unprotect feature allows code changes in
previously locked sectors
Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple program
command sequences
Top or Bottom Boot Block Configurations Available
Compatibility with JEDEC standards
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
Performance Characteristics
Ultra Low Power Consumption (typical values at 5 MHz)
Th
High Performance
– Access times as fast as 70 ns
– Extended temperature range (-40°C to +125°C)
Cypress Semiconductor Corporation
Document Number: 002-01232 Rev. *A
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
b l le
e te
fo d
r r an
ef d
er th
en e
ce
.
–
–
–
–
200 nA Automatic Sleep mode current
200 nA standby mode current
9 mA read current
20 mA program/erase current
Cycling Endurance: 1,000,000 cycles per sector typical
Data Retention: 20 years typical
Package Options
48-ball FBGA
48-pin TSOP
44-pin SOP
Software Features
CFI (Common Flash Interface) Compliant
– Provides device-specific information to the system, allowing host
software to easily reconfigure for different Flash devices
Erase Suspend/Erase Resume
– Suspends an erase operation to read data from, or program data
to, a sector that is not being erased, then resumes the erase
operation
Data# Polling and Toggle Bits
– Provides a software method of detecting program or erase
operation completion
Hardware Features
Ready/Busy# Pin (RY/BY#)
– Provides a hardware method of detecting program or erase cycle
completion
Hardware Reset Pin (RESET#)
– Hardware method to reset the device to reading array data
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 08, 2015
S29AL016D
General Description
The S29AL016D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered
in 48-ball FBGA, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on
DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt V
CC
supply. A 12.0 V V
PP
or 5.0
V
CC
are not required for write or erase operations. The device can also be programmed in standard EPROM programmers.
The device offers access times of 70 ns and 90 ns allowing high speed microprocessors to operate without wait states. To eliminate
bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
The device requires only a
single 3.0 volt power supply
for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The S29AL016D is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-
machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the
programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the
Embedded Program
algorithm—an
internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass
mode
facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the
Embedded Erase
algorithm—an internal
algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During
erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7
(Data# Polling) and DQ6 (toggle)
status bits.
After a program or erase cycle has been completed, the device is ready to read array
data or accept another command.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations during power
transitions. The
hardware sector protection
feature disables both program and erase operations in any combination of the sectors
of memory. This can be achieved in-system or via programming equipment.
The
Erase Suspend/Erase Resume
feature enables the user to put erase on hold for any period of time to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the internal state machine to reading array data. The
RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system
microprocessor to read the boot-up firmware from the Flash memory.
Spansion’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality,
reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim
tunneling. The data is programmed using hot electron injection.
Document Number: 002-01232 Rev. *A
Th
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters
the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly reduced in
both these modes.
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
b l le
e te
fo d
r r an
ef d
er th
en e
ce
.
Page 2 of 105
S29AL016D
Contents
Distinctive Characteristics
.................................................. 1
General Description
............................................................. 2
1.
2.
3.
3.1
4.
5.
6.
6.1
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
8.
8.1
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
10.
Product Selector Guide
............................................... 4
Block Diagram..............................................................
4
15.
16.
17.
17.1
17.2
17.3
17.4
17.5
17.6
18.
Test Conditions
........................................................... 35
Key to Switching Waveforms.....................................
36
AC Characteristics......................................................
37
Read Operations........................................................... 37
Hardware Reset (RESET#)........................................... 38
Word/Byte Configuration (BYTE#) ................................ 38
Erase/Program Operations ........................................... 40
Temporary Sector Unprotect......................................... 43
Alternate CE# Controlled Erase/Program Operations .. 44
Erase and Programming Performance
..................... 45
TSOP, SO, and BGA Pin Capacitance
....................... 46
Connection Diagrams..................................................
5
Special Handling Instructions......................................... 6
Pin Configuration.........................................................
6
Logic Symbol
............................................................... 7
Ordering Information
................................................... 7
S29AL016D Standard Products..................................... 7
Device Bus Operations................................................
8
Word/Byte Configuration................................................ 9
Requirements for Reading Array Data........................... 9
Writing Commands/Command Sequences.................... 9
Program and Erase Operation Status.......................... 10
Standby Mode.............................................................. 10
Automatic Sleep Mode................................................. 10
RESET#: Hardware Reset Pin..................................... 10
Output Disable Mode ................................................... 11
Autoselect Mode .......................................................... 14
Sector Protection/Unprotection .................................... 14
Temporary Sector Unprotect........................................ 15
Common Flash Memory Interface (CFI)
................... 20
Hardware Data Protection............................................ 22
Command Definitions................................................
Reading Array Data .....................................................
Reset Command ..........................................................
Autoselect Command Sequence .................................
Word/Byte Program Command Sequence...................
Unlock Bypass Command Sequence ..........................
Chip Erase Command Sequence ................................
Sector Erase Command Sequence .............................
Erase Suspend/Erase Resume Commands ................
Command Definitions................................................
27
Write Operation Status
..............................................
DQ7: Data# Polling ......................................................
RY/BY#: Ready/Busy#.................................................
DQ6: Toggle Bit I .........................................................
DQ2: Toggle Bit II ........................................................
Reading Toggle Bits DQ6/DQ2....................................
DQ5: Exceeded Timing Limits .....................................
DQ3: Sector Erase Timer.............................................
11.
11.1
11.2
11.3
11.4
11.5
11.6
11.7
12.
13.
Absolute Maximum Ratings......................................
32
Operating Ranges
...................................................... 32
14. DC Characteristics.....................................................
33
14.1 CMOS Compatible ....................................................... 33
14.2 Zero Power Flash......................................................... 34
Document Number: 002-01232 Rev. *A
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
b l le
e te
fo d
r r an
ef d
er th
en e
ce
.
19.
22
22
22
23
23
23
24
25
25
21.
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
28
28
29
30
30
30
31
31
20. Physical Dimensions
.................................................. 47
20.1 TS 048—48-Pin Standard TSOP .................................. 47
20.2 VBK048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 mm x 6.15 mm ......................................................48
20.3 SO044—44-Pin Small Outline Package (SOP)
28.20 mm x 13.30 mm ..................................................49
Revision Summary......................................................
50
Revision A (May 4, 2004).............................................. 50
Revision A1 (July 28, 2004) .......................................... 50
Revision A2 (December 17, 2004)................................ 50
Revision A3 (June 1, 2005)........................................... 50
Revision A4 (June 17, 2005)......................................... 51
Revision A5 (May 22, 2006).......................................... 51
Revision A6 (September 7, 2007)................................. 51
Revision A7 (November 27, 2007)................................ 51
Revision A8 (February 27, 2009) .................................. 51
Th
Page 3 of 53
S29AL016D
1.
Product Selector Guide
Family Part Number
Speed Option
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
Voltage Range: V
CC
= 2.7–3.6 V
70
70
70
S29AL016D
90
90
90
Max OE# access time, ns (t
OE
)
Note
See
AC Characteristics on page 37
for full specifications.
2. Block Diagram
RY/BY#
V
CC
V
SS
RESET#
WE#
BYTE#
CE#
OE#
A0–A19
Document Number: 002-01232 Rev. *A
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
b l le
e te
fo d
r r an
ef d
er th
en e
ce
.
30
35
DQ0
–
DQ15 (A-1)
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
STB
Y-Decoder
Y-Gating
Th
V
CC
Detector
Timer
Address Latch
X-Decoder
Cell Matrix
Page 4 of 53
S29AL016D
3.
Connection Diagrams
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
Document Number: 002-01232 Rev. *A
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
b l le
e te
fo d
r r an
ef d
er th
en e
ce
.
Standard TSOP
RESET#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Standard SOP
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
WE#
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
Th
Page 5 of 53
京公网安备 11010802033920号
EEWORLD
