K8S5615ET(B)A
NOR FLASH MEMORY
Document Title
256M Bit (16M x16) Muxed Burst , Multi Bank NOR Flash Memory
Revision History
Revision No. History
0.0
0.1
Preliminary
Revision
- Correct Device ID of Table 9 from 22F8h to 22FEh
- Change tCES ( CE Setup time to CLK ) from 9ns to 7ns at 54MHz
- Change tCES ( CE Setup time to CLK ) from 9ns to 6ns at 66MHz
- Change Accelerated Chip Erase time from 270sec to 240sec
- Modify the description of OTP Block
- Modify the size of OTP Block from 4KByte to 256Byte
- Remove "Autoselect OTP Block Factory Protect Verify" command
sequence
Draft Date
February 4, 2004
March 15, 2004
Remark
Preliminary
Preliminary
0.2
Revision
April 15, 2004
- Change Lower limit of Industrial Operating Temperature from -40
°C
to -25
°C
Revision
- Change the speed code
5A : 90ns @54MHz ---> 7B : 88.5ns @54MHz
5B : 70ns @66MHz ---> 7C : 70ns @66MHz
Revision
- Change the initial access time of asynchronous read mode
K8S5615ETA-DE7C
tAA : 70ns--->80ns
tCE : 70ns--->80ns
Revision
- Change the version ID
012Eh --> 012Dh
- Correct typo
Revision
- Specification finalized
- Correct typo
June 1, 2004
Preliminary
0.3
Preliminary
0.4
July 5, 2004
Preliminary
0.5
August 2, 2004
Preliminary
1.0
November 30, 2004
1.1
Revision
December 13, 2004
- Add the requirement and note of Quadruple word program operation
(Page24)
tAVDH is changed to 2ns
"Asynchronous mode may not support read following four sequential
invalid read condition within 200ns." is added
February 21, 2006
September 08, 2006
1.2
1.3
1
Revision 1.3
September, 2006
K8S5615ET(B)A
NOR FLASH MEMORY
256M Bit (16M x16) Muxed Burst , Multi Bank NOR Flash Memory
FEATURES
•
Single Voltage, 1.7V to 1.95V for Read and Write operations
•
Organization
- 16,777,216 x 16 bit ( Word Mode Only)
•
Multiplexed Data and Address for reduction of interconnections
- A/DQ0 ~ A/DQ15
•
Read While Program/Erase Operation
•
Multiple Bank Architecture
- 16 Banks (16Mb Partition)
•
OTP Block : Extra 256Byte block
•
Read Access Time (@ C
L
=30pF)
- Asynchronous Random Access Time :
90ns (54MHz) / 80ns (66MHz)
- Synchronous Random Access Time :
88.5ns (54MHz) / 70ns (66MHz)
- Burst Access Time :
14.5ns (54MHz) / 11ns (66MHz)
•
Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with No-wrap & Wrap
•
Block Architecture
- Eight 4Kword blocks and five hundreds eleven 32Kword
blocks
- Bank 0 contains eight 4 Kword blocks and thirty-one 32Kword
blocks
- Bank 1 ~ Bank 15 contain four hundred eighty 32Kword blocks
•
Reduce program time using the V
PP
•
Support Single & Quad word accelerate program
•
Power Consumption (Typical value, C
L
=30pF)
- Burst Access Current : 30mA
- Program/Erase Current : 15mA
- Read While Program/Erase Current : 40mA
- Standby Mode/Auto Sleep Mode : 25uA
•
Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=V
IL
- All blocks are protected by V
PP
=V
IL
•
Handshaking Feature
- Provides host system with minimum latency by monitoring
RDY
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program/Erase
•
Hardware Reset (RESET)
•
Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
•
Endurance
100K Program/Erase Cycles Minimum
•
Data Retention : 10 years
•
Extended Temperature : -25°C ~ 85°C
•
Support Common Flash Memory Interface
•
Low Vcc Write Inhibit
•
Package : 44 - ball FBGA Type, 8x11mm
0.5 mm ball pitch
1.0mm (Max.) Thickness
GENERAL DESCRIPTION
The K8S5615E featuring single 1.8V power supply is a 256Mbit
Muxed Burst Multi Bank Flash Memory organized as 16Mx16.
The memory architecture of the device is designed to divide its
memory arrays into 519 blocks with independent hardware pro-
tection. This block architecture provides highly flexible erase
and program capability. The K8S5615E NOR Flash consists of
sixteen banks. This device is capable of reading data from one
bank while programming or erasing in the other bank.
Regarding read access time, the K8S5615E provides an 14.5ns
burst access time and an 88.5ns initial access time at 54MHz.
At 66MHz, the K8S5615E provides an 11ns burst access time
and 70ns initial access time. The device performs a program
operation in units of Single 16 bits (word) and an erase opera-
tion in units of a block. Single or multiple blocks can be erased.
The block erase operation is completed within typically 0.7 sec.
The device requires 15mA as program/erase current in the
extended temperature ranges.
The K8S5615E NOR Flash Memory is created by using Sam-
sung's advanced CMOS process technology. This device is
available in 44 ball FBGA package.
PIN DESCRIPTION
Pin Name
A16 - A23
Pin Function
Address Inputs
A/DQ0 - A/DQ15 Multiplexed Address/Data input/output
CE
OE
RESET
V
PP
WE
WP
CLK
RDY
AVD
Vcc
V
SS
Chip Enable
Output Enable
Hardware Reset Pin
Accelerates Programming
Write Enable
Hardware Write Protection Input
Clock
Ready Output
Address Valid Input
Power Supply
Ground
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 1.3
September, 2006
Creative Market
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