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K4E640412D-TL450

Description
EDO DRAM, 16MX4, 45ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32
Categorystorage    storage   
File Size416KB,21 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
Download Datasheet Parametric View All

K4E640412D-TL450 Overview

EDO DRAM, 16MX4, 45ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32

K4E640412D-TL450 Parametric

Parameter NameAttribute value
MakerSAMSUNG
Parts packaging codeTSOP2
package instructionTSOP2,
Contacts32
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFAST PAGE WITH EDO
Maximum access time45 ns
Other featuresRAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/SELF REFRESH
JESD-30 codeR-PDSO-G32
length20.95 mm
memory density67108864 bit
Memory IC TypeEDO DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals32
word count16777216 words
character code16000000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16MX4
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Certification statusNot Qualified
Maximum seat height1.2 mm
self refreshYES
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width10.16 mm
K4E660412D,K4E640412D
CMOS DRAM
16M x 4bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 16,777,216 x 4 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Nor-
mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 16Mx4 EDO Mode DRAM family is fabricated
using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification
- K4E660412D-JC/L(3.3V, 8K Ref., SOJ)
- K4E640412D-JC/L(3.3V, 4K Ref., SOJ)
- K4E660412D-TC/L(3.3V, 8K Ref., TSOP)
- K4E640412D-TC/L(3.3V, 4K Ref., TSOP)
• Extended Data Out Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
Active Power Dissipation
Unit : mW
Speed
-45
-50
-60
Refresh Cycles
Part
NO.
K4E660412D*
K4E640412D
Refresh
cycle
8K
4K
Refresh time
Normal
64ms
L-ver
128ms
RAS
CAS
W
Control
Clocks
VBB Generator
Vcc
Vss
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V±0.3V power supply
4K
432
396
360
8K
324
288
252
FUNCTIONAL BLOCK DIAGRAM
Refresh Control
Refresh Counter
Memory Array
16,777,216 x 4
Cells
Sense Amps & I/O
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Performance Range
Speed
-45
-50
-60
Refresh Timer
Row Decoder
Data in
Buffer
DQ0
to
DQ3
Data out
Buffer
t
RAC
45ns
50ns
60ns
t
CAC
12ns
13ns
15ns
t
RC
74ns
84ns
104ns
t
HPC
17ns
20ns
25ns
A0~A12
(A0~A11)*1
A0~A10
(A0~A11)*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
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