LX1801ILQ datasheet, PDF - EEWORLD Datasheet

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LX1801ILQ: DescriptionAnalog Circuit, 1 Func, 3 X 3 MM, ROHS COMPLIANT, MLPQ-16; CategoryAnalog mixed-signal IC The signal circuit; File Size684KB，12 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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LX1801ILQ Overview

Analog Circuit, 1 Func, 3 X 3 MM, ROHS COMPLIANT, MLPQ-16

LX1801ILQ Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microsemi
Parts packaging code	QFN
package instruction	HVQCCN,
Contacts	16
Reach Compliance Code	compliant
Analog Integrated Circuits - Other Types	ANALOG CIRCUIT
JESD-30 code	S-XQCC-N16
JESD-609 code	e3
length	3 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	3 mm

LX1801ILQ Preview

LX1801

SMBus to Analog & Digital System Interface

RODUCTION

ATA

HEET

DESCRIPTION

KEY FEATURES

Fully Compliant to Standard

SMBus Specifications

I2C Bus Compatible

8 bit Resolution

±10 LSB Accuracy

One 8 bit ADC

Three 8 bit DAC’s

SMBus Address Strap for 2

Selectable Addresses

External Reference Inputs Set

Analog Brightness Voltage

Lower Limit and Range

APPLICATIONS

IMPORTANT:

For the most current data, consult

MICROSEMI’s

website:

http://www.microsemi.com

LX1972

Part

ALS

ALS_IN

SDA

SCL

I/O

CONN

SMB_DAT

SMB_CLK

INV_PWM

Notebook LCD inverter with 5 SMBus dimming modes including bus driven, ambient light sensor driven, PWM driven, and either SMBus or ALS

with Intel

DPST enhancement.

PRODUCT HIGHLIGHT

LX1801

V_BOT

VREF_IN

VDD

VSS

LX169x Based

CCFL Inverter

PWM_IN

VSS

Part

OVR_CUR

LMP_ON

LMP_C

FLT_DLY

EN_OUT

BRITE_OUT

ADR0

The LX1801 is a SMBus controlled

dimming interface for CCFL inverters.

It complies with the Dell Inc. M07

specification for Notebook backlight

inverters.

The LX1801 processes 3 brightness

control inputs, one each from the

SMBus, an ambient light sensor, and a

separate system side PWM signal and

generates an analog output signal that

drives the dimming circuitry of a

CCFL inverter controller.

Five

different brightness control modes are

supported which include Intel DPST

display power saving technology.

In addition to its SMBus interface,

the LX1801 contains an eight bit ADC,

seven 8 bit registers, three 8 bit DAC’s,

a multiplier, and other special circuits

that process its analog voltage output.

The LX1801 controls inverter on/off

and monitors and reports lamp status

and inverter faults in real time.

The LX1801 is available in the 16

lead 3 x 3mm MLPQ package.

WWW .

Microsemi

Processor and Ambient Light

Senor (ALS) Controlled LCD

Panel Dimming with Intel DPST

General Purpose SMBus I/O

Control Applications

LX1801

PACKAGE ORDER INFO

(°C)

-40 to 85

Plastic 3x3 mm MLPQ 16 pin

RoHS Compliant / Pb-free

LX1801ILQ

Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1801ILQ-TR)

2005

Rev. 1.1, 7/7/2006

Microsemi

Integrated Products Division

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

Page 1

LX1801

SMBus to Analog & Digital System Interface

RODUCTION

ATA

HEET

ABSOLUTE MAXIMUM RATINGS

PACKAGE PIN OUT

WWW .

Microsemi

Supply Input Voltage ........................................................................-0.3V to 7.0V

Input and Output Pins .......................................................................-0.3V to 7.0V

Operating Temperature Range. ……………………………………...-40 to 85°C

Maximum Operating Junction Temperature ................................................ 150°C

Storage Temperature Range...........................................................-65°C to 150°C

Peak Package Solder Reflow Temp (40 seconds max. exposure)..... 260°C(+0,-5)

Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to

Ground. Currents are positive into, negative out of specified terminal

V_BOT

VREF_IN

ADR0

VDD

ALS_IN

SDA

SCL

PWM_IN

VSS

FLT_DLY

EN_OUT

BRITE_OUT

THERMAL DATA

Junction Temperature Calculation: T

= T

+ (P

The

numbers are guidelines for the thermal performance of the device/pc-board system. All of the

above assume no ambient airflow.

ACKAGE

ATA

ACKAGE

ATA

2005

Rev. 1.1, 7/7/2006

Microsemi

Plastic 3x3 mm MLPQ 16-Pin

THERMAL RESISTANCE

JUNCTION TO

MBIENT

VSS

OVR_CUR

LQ P

ACKAGE

(Top View)

33.3°C/W

RoHS / Pb-free 100% Matte Tin Lead Finish

LMP_ON

LMP_C

Integrated Products Division

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

Page 2

LX1801

SMBus to Analog & Digital System Interface

RODUCTION

ATA

HEET

FUNCTIONAL PIN DESCRIPTION

Name

VDD

VSS

SCL

SDA

ADR0

ALS_IN

PWM_IN

VREF_IN

V_BOT

Power Supply Input: 4.5V to 5.5V

Ground (2 Pins)

Digital Input. SMBus Clock – 10 to 100 KHz capable

Digital I/O. SMBus Data – SMBus Data line

SMBus Address strap input – The address for the LX1801 is determined by the state of this pin (see table 1).

Analog input. Ambient light sensor input. Zero to VREF_IN range.

Description

WWW .

Microsemi

Analog Input reference voltage for ADC and DAC. Operating range is 1.5 to 3 Vdc. Nominal input is 2.040V.

Input impedance is greater than 10MΩ.

An analog voltage input whose value determines the minimum output voltage of BRITE_OUT after the effect

of the PWM input when in DPST mode and at all times in other modes.

BRITE_OUT

LMP_C

Lamp Capacitor. A capacitor, typically 10nF and a resistor, typically 1MΩ, are connected in parallel from

this pin to ground. They filter a peak voltage detector with the LMP_ON input.

Analog / Digital input to comparator and latch. Used for over current status input in M07 application. 1.2V

threshold. If OVR_CUR > 1.2V

, a “1” is latched and written to bit 0 (FAULT) and bit 2(OV_CURR) of the

fault status register (Register 0x02). The latched bits can only be cleared by a write byte command to

LAMP_CTL bit in register 0x01, causing the enable output to the CCFL controller (EN_OUT) to go low and

turn off the inverter. Zero to VDD input voltage range.

Digital input. Approximately 1V threshold. When LMP_ON is “1” it charges the capacitor at pin LMP_C to

VDD, indicating the lamp is turned on. This pin is normally connected to the A_OUT pin of the LX1692 / 93

controller, and will cause internal circuitry to report the lamp is on if there are pulses on A_OUT. If these

pulses stop long enough for the voltage at LMP_C to decrease below 1.2 V, the lamp is reported off at bit

03 of the FLT/STAT register (0x02). . If LAMP_CTL transitions to high, requesting the inverter to turn on, and

LMP_C does not go above 1.2V before the FLT_DLY pin reaches 2.5V, an open lamp error signal is

produced and is stored, along with other error conditions, to bit zero of the FLT STATUS register 0x02. An

Open lamp fault will cause EN_OUT to go low. See FLT_DLY description. Zero to VDD input voltage range

Analog / Digital input to the open lamp comparator and latch. This input provides for a time out before

LMP_ON is sensed for an open lamp fault. The comparator has a 2.5V threshold. The comparator output is

latched when 2.5V is exceeded. The latch is reset at power on and when EN_OUT transitions to high. This

pin is normally connected to the C_TO pin of the LX1692 or 1693 CCFL controller.

Digital Output. Enable output to CCFL controller. TTL voltage and current levels. EN_OUT is made high or

low by a write byte command to register 0x01. It is also reset by bit zero of register 0x02 going high.

OVR_CUR

LMP_ON

FLT_DLY

EN_OUT

Microsemi

Analog output voltage that is equal to desired BRITE_OUT voltage after modulation by the PWM input and

offset by the voltage at the V_BOT input. An R/C filter at this pin to low pass filters the signal and determines

response time when in PWM and DPST modes. In PWM and DPST modes, the output voltage is modulated

on and off at the duty cycle and frequency of PWM_IN. The R/C filter is comprised of an internal 100K

resistor and an external capacitor to ground.

A digital input from the system controller whose duty cycle determines lamp brightness when in PWM mode,

and multiplies lamp brightness by a fractional value equal to its duty cycle when in DPST mode.

ACKAGE

ATA

ACKAGE

ATA

2005

Rev. 1.1, 7/7/2006

Integrated Products Division

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

Page 3

LX1801

SMBus to Analog & Digital System Interface

RODUCTION

ATA

HEET

Unless otherwise specified, the following specifications apply over the operating ambient temperature -40°C

≤

otherwise noted and the following test conditions: V

= 5V + 10 / -5%.

Parameter

Symbol

Test Conditions

ELECTRICAL CHARACTERISTICS

≤

85°C except where

WWW .

Microsemi

Min

4.5

1.0

-9

-2

97% *

VREF

-3

-4

LX1801

Typ

2.5

Max

5.5

4.0

103% *

VREF

Units

Bits

LSB

% of

Ideal

Bits

LSB

Bits

Full Scale Output Voltage

Offset Error

Gain Error

FSV

CODE = 255, -10nA < IOUT < 10nA

CODE = 0, -10nA < IOUT < 10nA

-10nA < IOUT < 10nA

FSV

I_leak

INL

DNL

LOW LIMIT CLAMP DAC DC PERFORMANCE

Resolution

Low Limit DAC CODE = 15 to 205, High Limit DAC

Relative Accuracy (Note 1)

CODE > 50 LSB above Low Limit DAC CODE

Low Limit DAC CODE = 0, High Limit DAC CODE >

Offset Error

50 LSB above Low Limit DAC CODE

HIGH LIMIT CLAMP DAC DC PERFORMANCE

Resolution

High Limit DAC CODE = 50 to 232, Low Limit DAC

Relative Accuracy (Note 2)

CODE = 50 LSB below High Limit DAC CODE

ALS MODE ACCURACY

Low Limit DAC CODE = 15 to 205, High Limit DAC

Output Error at BRITE_OUT

Code > 50 LSB above Low Limit DAC CODE,

ALS_IN = 20% * VREF to 80% * VREF. VBOT = 0V

ADC

Resolution

Resolvable Input Range

Full Scale Output Voltage

Input Leakage Current (ALS_IN)

Integral Nonlinearity

Differential Nonlinearity

Offset Error

Gain Error

ALS_IN = 0V to VDD

Only Major Carry Codes Tested

ALS_IN = 0V

ALS_IN = VREF; Read Register. 4

-10

-1

-7

97% *

VREF

-1

-2

-3

VREF

±3

±1.5

VREF

103% *

VREF

POWER SUPPLY

Operating Supply Voltage

VDD

Average Supply Current

IDD

DAC = FFH; idle ADC

BRIGHTNESS CONTROL DAC DC PERFORMANCE

Resolution

Integral Nonlinearity

INL

CODE = 0 to 255, -10nA < IOUT < 10nA

Differential Nonlinearity

DNL

CODE = 0 to 255, -10nA < IOUT < 10nA

LSB

% of

ALS_IN

Bits

µA

LSB

% of

FSR

REF_IN

Reference Voltage

REF

1.80

2.040

3.00

Input Leakage Current

REF

-50

ADR

High Level Input Voltage

AHL

%VDD

Low Level Input Voltage

ALL

%VDD

Input Leakage Current

ADR

-50

SCL, SDA, PWM

High Level Input Voltage

SHL

2.1

Low Level Input Voltage

SLL

0.8

Input Leakage Current

SMB

-5

µA

SDA Low Level Output Voltage

IOUT = 3mA

0.4

SMBUS

SMB clock frequency

CLK

100

KHz

Note 1: The Relative Accuracy of the Low Limit DAC is specified to be the deviation from the ideal programmed value: Ideal = VREF * (CODE/255).

The Relative Accuracy is specified for the range CODE = 15 to 205

Note 2: The Relative Accuracy of the High Limit DAC is specified to be the deviation from the ideal programmed value: Ideal = VREF * (CODE/255).

The Relative Accuracy is specified for the range CODE = 50 to 232

LECTRICALS

2005

Rev. 1.1, 7/7/2006

Microsemi

Integrated Products Division

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

Page 4

LX1801

SMBus to Analog & Digital System Interface

RODUCTION

ATA

HEET

APPLICATION NOTE

The LX1801 is a seven register device that uses SMBus

commands to communicate with the host system. All registers are

defined as full byte wide with reserved (undefined) bits containing a

default value of “0”. Four of the seven registers are read / write, and

three are read only with respect to the SMBus.

SMB PROTOCOL

Only standard SMBus protocol, version 2.0 or higher, may be

used for this device. The only required commands are the SMBus

Read Byte and the SMBus Write Byte protocols. There are to be no

non standard protocols implemented. Further, register contents shall

not be altered by invalid commands.

General Rules for Writing and Reading LX1801 Registers with

the SMBus.

Writes to registers can be performed by either the SMBus Write

Byte protocol and / or by internal IC logic, depending on the register

type (see table 1).

Reads can be performed on all seven registers by issuing the

Read_Byte protocol.

Read Only registers can be written only by internal logic. Their

contents can not be affected by SMBus write commands.

Specific Requirements for SMBus Protocols:

WWW .

Microsemi

Read Byte Protocol:

Slave Address

Command Code

Slave Address

Command Code

Data Byte

•

The IC shall implement the SMBus Read Byte protocol.

•

The IC shall implement the SMBus Write Byte protocol.

•

The IC shall not require the use of any other SMBus protocol to

meet the requirements contained in the Dell M07 specification.

•

The IC shall operate correctly when the SMBus master clock

operates at a frequency of 55KHz and over the complete

frequency range of 10KHz to 100KHz.

•

The IC shall not employ clock stretching.

•

The IC shall not include SMBus pull up resistors. These are

provided by the host system.

Write Byte Protocol:

Slave Address

Grey shading represents cycles during which the LX1801 “owns” or “drives” the Data line. All other cycles are driven by the host.

Definitions

Wr:

Rd:

Start condition

Write

Read

Acknowledge

Stop Condition

Protocol must be per standard SMB specification version 2.0 or higher.

PPLICATIONS

2005

Rev. 1.1, 7/7/2006

Microsemi

Integrated Products Division

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

Page 5

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