Energy Metering IC
with Integrated Oscillator
ADE7757
*
FEATURES
On-Chip Oscillator as Clock Source
High Accuracy, Supposes 50 Hz/60 Hz IEC 521/IEC 61036
Less than 0.1% Error over a Dynamic Range of 500 to 1
The ADE7757 Supplies Average Real Power on the
Frequency Outputs F1 and F2
The High Frequency Output CF Is Intended for
Calibration and Supplies Instantaneous Real Power
The Logic Output REVP Can Be Used to Indicate a
Potential Miswiring or Negative Power
Direct Drive for Electromechanical Counters and
2-Phase Stepper Motors (F1 and F2)
Proprietary ADCs and DSP Provide High Accuracy over
Large Variations in Environmental Conditions and
Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V (20 ppm/ C Typical)
with External Overdrive Capability
Single 5 V Supply, Low Power (20 mW Typical)
Low Cost CMOS Process
AC Input Only
GENERAL DESCRIPTION
built with this IC. The chip directly interfaces with the shunt
resistor and operates only with ac input.
The ADE7757 specifications surpass the accuracy requirements
as quoted in the IEC 61036 standard. The AN-679 Application
Note can be used as a basis for a description of an IEC 61036
low cost watt-hour meter reference design.
The only analog circuitry used in the ADE7757 is in the -
ADCs and reference circuit. All other signal processing (e.g.,
multiplication and filtering) is carried out in the digital domain.
This approach provides superior stability and accuracy over
time and extreme environmental conditions.
The ADE7757 supplies average real power information on the
low frequency outputs F1 and F2. These outputs may be used
to directly drive an electromechanical counter or interface with
an MCU. The high frequency CF logic output, ideal for calibra-
tion purposes, provides instantaneous real power information.
The ADE7757 includes a power supply monitoring circuit on
the V
DD
supply pin. The ADE7757 will remain inactive until
the supply voltage on V
DD
reaches approximately 4 V. If the
supply falls below 4 V, the ADE7757 will also remain inactive
and the F1, F2, and CF outputs will be in their nonactive modes.
Internal phase matching circuitry ensures that the voltage and
current channels are phase matched while the HPF in the cur-
rent channel eliminates dc offsets. An internal no-load threshold
ensures that the ADE7757 does not exhibit creep when no load
is present.
The ADE7757 is available in a 16-lead SOIC narrow-body package.
The ADE7757 is a high accuracy electrical energy measurement
IC. It is a pin reduction version of the ADE7755 with an enhance-
ment of a precise oscillator circuit that serves as a clock source
to the chip. The ADE7757 eliminates the cost of an external
crystal or resonator, thus reducing the overall cost of a meter
FUNCTIONAL BLOCK DIAGRAM
V
DD
AGND
DGND
ADE7757
POWER
SUPPLY MONITOR
V2P
V2N
...110101...
MULTIPLIER
PHASE
CORRECTION HPF
...11011001...
SIGNAL
PROCESSING
BLOCK
LPF
-
ADC
V1N
V1P
-
ADC
2.5V
REFERENCE
4k
INTERNAL
OSCILLATOR
DIGITAL-TO-FREQUENCY
CONVERTER
REF
IN/OUT
RCLKIN
SCF
S0
S1 REVP CF
F1
F2
*U.S.
Patents
5,745,323; 5,760,617; 5,862,069; 5,872,469.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
(V
5%, AGND
0 V,
RCLKIN 6.2 k
ADE7757–SPECIFICATIONS
0.5%= 5 V50 ppm/ C, T =toDGND==–40 COn-Chip Reference,otherwise=noted.) ,
T
to +85 C, unless
DD
MIN
MAX
Parameter
ACCURACY
1, 2
Measurement Error
1
on Channel V1
Value
Unit
Test Conditions/Comments
Channel V2 with Full-Scale Signal (± 165 mV), 25°C
Over a Dynamic Range 500 to 1
Line Frequency = 45 Hz to 65 Hz
0.1
Phase Error between Channels
V1 Phase Lead 37°
(PF = 0.8 Capacitive)
V1 Phase Lag 60°
(PF = 0.5 Inductive)
AC Power Supply Rejection
1
Output Frequency Variation (CF)
DC Power Supply Rejection
1
Output Frequency Variation (CF)
ANALOG INPUTS
Channel V1 Maximum Signal Level
Channel V2 Maximum Signal Level
Input Impedance (DC)
Bandwidth (–3 dB)
ADC Offset Error
1, 2
Gain Error
1
OSCILLATOR FREQUENCY (OSC)
Oscillator Frequency Tolerance
1
Oscillator Frequency Stability
1
REFERENCE INPUT
REF
IN/OUT
Input Voltage Range
Input Capacitance
ON-CHIP REFERENCE
Reference Error
Temperature Coefficient
LOGIC INPUTS
3
SCF, S0, S1,
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN
LOGIC OUTPUTS
3
F1 and F2
Output High Voltage, V
OH
4.5
Output Low Voltage, V
OL
0.5
CF
Output High Voltage, V
OH
4
Output Low Voltage, VOL
Frequency Output Error
POWER SUPPLY
V
DD
I
DD
1, 2
1
% Reading typ
±
0.1
±
0.1
0.2
±
0.3
Degrees (°) max
Degrees (°) max
% Reading typ
S0 = S1 = 1,
V1 = 21.2 mV rms, V2 = 116.7 mV rms @ 50 Hz
Ripple on V
DD
of 200 mV rms @ 100 Hz
S0 = S1 = 1,
V1 = 21.2 mV rms, V2 = 116.7 mV rms,
V
DD
= 5 V
±
250 mV
See Analog Inputs section
V1P and V1N to AGND
V2P and V2N to AGND
OSC = 450 kHz, RCLKIN = 6.2 kΩ, 0.5%
±
5
0
ppm/°C
OSC = 450 kHz, RCLKIN = 6.2 kΩ, 0.5%
±
50 ppm/°C
See Terminology Section and Typical Performance Characteristics
External 2.5 V Reference
V1 = 21.2 mV rms, V2 = 116.7 mV rms
RCLKIN = 6.2 kΩ, 0.5%
±
50 ppm/°C
% Reading typ
±
30
±
165
320
7
±
18
±
4
450
±
12
±
30
2.7
2.3
10
±
200
±
20
mV max
mV max
kΩ min
kHz nominal
mV max
% Ideal typ
kHz nominal
% Reading typ
ppm/°C typ
V max
V min
pF max
mV max
ppm/°C typ
2.5 V + 8%
2.5 V – 8%
Nominal 2.5 V
2.4
0.8
±
1
10
V min
V max
µA
max
pF max
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
Typically 10 nA, V
IN
= 0 V to V
DD
V min
V max
I
SOURCE
= 10 mA
V
DD
= 5 V
I
SINK
= 10 mA
V
DD
= 5 V
I
SOURCE
= 5 mA
V
DD
= 5 V
I
SINK
= 5 mA
V
DD
= 5 V
External 2.5 V Reference,
V1 = 21.2 mV rms, V2 = 116.7 mV rms
For Specified Performance
5 V – 5%
5 V + 5%
Typically 4 mA
V min
V max
% Ideal typ
(CF)
0.5
±
10
4.75
5.25
5
V min
V max
mA max
NOTES
1
See Terminology section for explanation of specifications.
2
See plots in Typical Performance Characteristics.
3
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
–2–
REV. A
ADE7757
TIMING CHARACTERISTICS
Parameter
t
13
t
2
t
3
t
43, 4
t
5
t
6
A, B Versions
244
See Table II
1/2 t
2
173
See Table III
2
1, 2
(V
DD
= 5 V
0.5%
5%, AGND = DGND = 0 V, On-Chip Reference, RCLKIN = 6.2 kΩ,
50 ppm/ C, T
MIN
to T
MAX
= –40 C to +85 C, unless otherwise noted.)
Test Conditions/Comments
F1 and F2 Pulse Width (Logic Low).
Output Pulse Period. See Transfer Function section.
Time between F1 Falling Edge and F2 Falling Edge.
CF Pulse Width (Logic High).
CF Pulse Period. See Transfer Function section.
Minimum Time between F1 and F2 Pulses.
Unit
ms
sec
sec
ms
sec
µs
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter.
2
See Figure 1.
3
The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See Frequency Outputs section.
4
The CF pulse is always 35
µs
in the high frequency mode. See Frequency Outputs section and Table III.
Specifications subject to change without notice.
t
1
F1
t
6
t
2
F2
t
3
t
4
t
5
CF
Figure 1. Timing Diagram for Frequency Outputs
REV. A
–3–
ADE7757
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C, unless otherwise noted.)
Power Supply Rejection
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to AGND
V1P, V1N, V2P, and V2N . . . . . . . . . . . . . . . . –6 V to +6 V
Reference Input Voltage to AGND . . . –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
16-Lead Plastic SOIC, Power Dissipation . . . . . . . . . 350 mW
2
. . . . . . . . . . . . . . . . . . . 124.9°C/W
JA
Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
JEDEC 1S Standard (2-layer) Board Data.
This quantifies the ADE7757 measurement error as a percent-
age of reading when the power supplies are varied.
For the ac PSR measurement, a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading is obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of reading—see the Measurement Error definition.
For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. The supplies are then varied
±
5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.
ADC Offset Error
This refers to the small dc signal (offset) associated with the
analog inputs to the ADCs. However, the HPF in Channel V1
eliminates the offset in the circuitry. Therefore, the power cal-
culation is not affected by this offset.
Frequency Output Error (CF)
The frequency output error of the ADE7757 is defined as the
difference between the measured output frequency (minus
the offset) and the ideal output frequency. The difference is
expressed as a percentage of the ideal frequency. The ideal
frequency is obtained from the ADE7757 transfer function
(see the Transfer Function section).
Gain Error
ORDERING GUIDE
Model
ADE7757ARN
ADE7757ARNRL
Package Description Package Options
RN-16
RN-16
Evaluation Board
Reference Design
SOIC Narrow-Body
SOIC Narrow-Body
in Reel
EVAL-ADE7757EB Evaluation Board
ADE7757ARN-REF Reference Design
TERMINOLOGY
Measurement Error
The gain error of the ADE7757 is defined as the difference
between the measured output frequency (minus the offset) and
the ideal output frequency. The difference is expressed as a
percentage of the ideal frequency. The ideal frequency is obtained
from the ADE7757 transfer function (see the Transfer Function
section).
Oscillator Frequency Tolerance
The error associated with the energy measurement made by the
ADE7757 is defined by the following formula
The oscillator frequency tolerance of the ADE7757 is defined as
part-to-part frequency variation in terms of percentage at room
temperature (25°C). It is measured by taking the difference
between the measured oscillator frequency and the nominal
frequency defined in the Specifications section.
Oscillator Frequency Stability
%
Error
=
Energy Registered by ADE
7757–
True Energy
¥
100%
True Energy
Phase Error between Channels
The HPF (high-pass filter) in the current channel (Channel V1)
has a phase lead response. To offset this phase response and
equalize the phase response between channels, a phase correc-
tion network is also placed in Channel V1. The phase correction
network matches the phase to within
±0.1°
over a range of 45 Hz
to 65 Hz, and
±
0.2° over a range 40 Hz to 1 kHz (see Figures
11 and 12).
Oscillator frequency stability is defined as frequency variation
in terms of parts-per-million drift over the operating tem-
perature range. In a metering application, the temperature
range is –40°C to +85°C. Oscillator frequency stability is
measured by taking the difference between the measured
oscillator frequency at –40°C and +85°C and the measured
oscillator frequency at +25°C.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADE7757 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. A
ADE7757
PIN CONFIGURATION
V
DD 1
V2P
2
16
15
14
F1
F2
CF
V2N
3
V1N
4
13
DGND
TOP VIEW
V1P
5
(Not to Scale)
12
REVP
11
RCLKIN
AGND
6
ADE7757
REF
IN/OUT 7
SCF
8
10
9
S0
S1
PIN FUNCTION DESCRIPTIONS
Pin No.
1
Mnemonic
V
DD
Description
Power Supply. This pin provides the supply voltage for the circuitry in the ADE7757. The supply voltage
should be maintained at 5 V
±
5% for specified operation. This pin should be decoupled with a 10
µF
capacitor in parallel with a ceramic 100 nF capacitor.
Analog Inputs for Channel V2 (voltage channel). These inputs provide a fully differential input pair. The
maximum differential input voltage is
±
165 mV for specified operation. Both inputs have internal ESD
protection circuitry; an overvoltage of
±
6 V can be sustained on these inputs without risk of permanent
damage.
Analog Inputs for Channel V1 (current channel). These inputs are fully differential voltage inputs with a
maximum signal level of
±
30 mV with respect to the V1N pin for specified operation. Both inputs have
internal ESD protection circuitry and, in addition, an overvoltage of
±
6 V can be sustained on these
inputs without risk of permanent damage.
This provides the ground reference for the analog circuitry in the ADE7757, i.e., ADCs and reference.
This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground
reference for all analog circuitry, e.g., antialiasing filters, current and voltage sensors, and so forth. For
accurate noise suppression, the analog ground plane should be connected to the digital ground plane at
only one point. A star ground configuration will help to keep noisy digital currents away from the analog
circuits.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value
of 2.5 V and a typical temperature coefficient of 20 ppm/°C. An external reference source may also
be connected at this pin. In either case, this pin should be decoupled to AGND with a 1
µF
tanta-
lum capacitor and a 100 nF ceramic capacitor. The internal reference cannot be used to drive an
external load.
Select Calibration Frequency. This logic input is used to select the frequency on the calibration output
CF. Table III shows calibration frequencies selection.
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conver-
sion. With this logic input, designers have greater flexibility when designing an energy meter. See the
Selecting a Frequency for an Energy Meter Application section.
To enable the internal oscillator as a clock source to the chip, a precise low temperature drift resistor at a
nominal value of 6.2 kΩ must be connected from this pin to DGND.
This logic output will go high when negative power is detected, i.e., when the phase angle between the
voltage and current signals is greater than 90°. This output is not latched and will be reset when positive
power is once again detected. The output will go high or low at the same time that a pulse is issued on CF.
This provides the ground reference for the digital circuitry in the ADE7757, i.e., multiplier, filters, and
digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The digi-
tal ground plane is the ground reference for all digital circuitry, e.g., counters (mechanical and digital),
MCUs, and indicator LEDs. For accurate noise suppression, the analog ground plane should be con-
nected to the digital ground plane at one point only, i.e., a star ground.
Calibration Frequency Logic Output. The CF logic output provides instantaneous real power informa-
tion. This output is intended for calibration purposes. Also see SCF pin description.
Low Frequency Logic Outputs. F1 and F2 supply
average real power
information. The logic outputs can
be used to directly drive electromechanical counters and 2-phase stepper motors. See the Transfer Func-
tion section.
–5–
2, 3
V2P, V2N
4, 5
V1N, V1P
6
AGND
7
REF
IN/OUT
8
9, 10
SCF
S1, S0
11
12
RCLKIN
REVP
13
DGND
14
15, 16
CF
F2, F1
REV. A
Embedded System
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