- Register table name changed : Reset Value -> Default Value
- Register default value changed
- Typing error corrected
- FEATURES updated
- Register map summary table added.
- Typing error corrected (I
2
C continuous read/write removal)
- Functional description added (GrGb correction)
- Register default value changed.
- Register map description updated.
- [NOTE] at Figure 12 about CIS raw data timing is modified.
- [NOTE] at Figure 15 and Figure 16 about I
2
C R/W is modified.
- SCL clock frequency updated @ Figure 14
- Table 4. DC characteristics updated.
(QVGA preview mode power consumption is updated to 65mW)
- Power Up Sequence is modified ( Page 25 )
- Table 4. DC characteristics updated.
(QVGA preview mode power consumption is updated to
TYP. 60mW)
- Page 9, Table1 is modified (D9~D8)
- Page 12, CIS raw data output decription is modified
- Page 20, CIS only raw data output timing is added.
- Page 24, 25, I
2
C Read/Write Timing
Maximum T8 is modified to 15000 cycles
0.10
04-12-13
Y.T. Jang
0.11
0.12
0.13
04-12-22
05-01-03
05-01-07
J.T. Joo
J.T. Joo
J.T. Joo
0.14
05-01-21
Y.T. Jang
0.15
05-02-08
M.S. Kim
0.20
0.21
0.22
0.23
05-03-04
05-04-18
05-06-03
05-07-02
M.S. Kim
M.S. Kim
J.T. Joo
J.Y. Yang
Y.T. Jang
0.24
05-07-11
Y.T. Jang
0.25
05-08-31
Y.T. Jang
0.26
05-09-28
Y.T. Jang
SAMSUNG PROPRIETARY
EVT6-R030
2/45
S5K3AAEX – 1/3.2 INCH SXGA CIS WITH ISP
PRELIMINARY DATA SHEET
0.27
0.28
0.29
0.30
05-10-26
05-11-02
05-12-23
05-12-28
Y.T. Jang
Y.T. Jang
M.J.Shin
Y.T. Jang
Y.T. Jang
- Page 23, [Note] for SCL clock frequency is added.
SCL/SDA rise/fall time added
- Page 26, Power up sequence modified
30ms -> 600000 cycles
- Page 26, Figure 17, 18 are modified
VDDIO power sequence is added.
- Page 22, output data and pixel clock timing is modified
- Table 5, AC characteristics is modified
- BPR Description in Sensor Only mode updated
- Page 24,25 I
2
C R/W timing modified,
T9 (ACK to ACK period) time is added.
- Page 24, 25 I
2
C R/W timing modified,
T10 (ACT to STOP period) time is added.
SAMSUNG PROPRIETARY
EVT6-R030
3/45
S5K3AAEX – 1/3.2 INCH SXGA CIS WITH ISP
PRELIMINARY DATA SHEET
Contents
Document Revision History .....................................................................................................................................2
Features ..................................................................................................................................................................2
General Description.................................................................................................................................................2
Pad Configuration....................................................................................................................................................2
Pixel Array Information ............................................................................................................................................2
Serial Host Interface ................................................................................................................................................2
Power Up/Down Sequence .....................................................................................................................................2
Figure 2: Pad Configuration........................................................................................................................................2
Figure 3: Pixel Array Information ................................................................................................................................2
Figure 6: Bayer Space Sub-Sampling Examples........................................................................................................2
Figure 7: Relative Channel Gain ................................................................................................................................2
Figure 8: Recommended Minimum Global Gain Control Value..................................................................................2
Figure 9: ITU-R.601 YCbCr Data Output Timing ........................................................................................................2
Figure 10: ITU-R.656 YCbCr Data Output Timing ......................................................................................................2
Figure 11: 565RGB Data Output Timing .....................................................................................................................2
Figure 12: CIS Raw Data Output Timing ....................................................................................................................2
Figure 13: Video Output Timing and Pixel Clock Timing ............................................................................................2
Figure 14: I
2
C General Timing ....................................................................................................................................2
Figure 15: I
2
C Write Timing.........................................................................................................................................2
Figure 16: I
2
C Read Timing ........................................................................................................................................2
Figure 17: Power Up Sequence..................................................................................................................................2
Figure 18: Power Down Sequence.............................................................................................................................2
Table 2: Minimum Global Gain Setting according to Main Clock Frequency .............................................................2
Table 3: Absolute Maximum Ratings ..........................................................................................................................2
Table 4: DC Characteristics ........................................................................................................................................2
Table 5: AC Characteristics.........................................................................................................................................2
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