IC EE PLD, 25 ns, CDIP20, CERAMIC, DIP-20, Programmable Logic Device
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | National Semiconductor（TI ） |
| package instruction | DIP, DIP20,.3 |
| Reach Compliance Code | unknown |
| Other features | POWER-UP RESET; REGISTER PRELOAD |
| Architecture | PAL-TYPE |
| maximum clock frequency | 28.5 MHz |
| JESD-30 code | R-GDIP-T20 |
| JESD-609 code | e0 |
| length | 24.51 mm |
| Dedicated input times | 8 |
| Number of I/O lines | 8 |
| Number of entries | 18 |
| Output times | 8 |
| Number of product terms | 64 |
| Number of terminals | 20 |
| Maximum operating temperature | 85 °C |
| Minimum operating temperature | -40 °C |
| organize | 8 DEDICATED INPUTS, 8 I/O |
| Output function | MACROCELL |
| Package body material | CERAMIC, GLASS-SEALED |
| encapsulated code | DIP |
| Encapsulate equivalent code | DIP20,.3 |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| power supply | 5 V |
| Programmable logic type | EE PLD |
| propagation delay | 25 ns |
| Certification status | Not Qualified |
| Maximum seat height | 5.08 mm |
| Maximum supply voltage | 5.5 V |
| Minimum supply voltage | 4.5 V |
| Nominal supply voltage | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | INDUSTRIAL |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| width | 7.62 mm |
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