MN74HC51S datasheet, PDF - EEWORLD Datasheet

MN74HC51S: DescriptionAND-OR-Invert Gate, HC/UH Series, 2-Func, 6-Input, CMOS, PDSO14, SOP-14; Categorylogic logic; File Size64KB，2 Pages; ManufacturerPanasonic; Websitehttp://www.panasonic.co.jp/semicon/e-index.html

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MN74HC51S Overview

AND-OR-Invert Gate, HC/UH Series, 2-Func, 6-Input, CMOS, PDSO14, SOP-14

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Panasonic
Parts packaging code	SOIC
package instruction	SOP-14
Contacts	14
Reach Compliance Code	unknown
series	HC/UH
JESD-30 code	R-PDSO-G14
JESD-609 code	e0
Load capacitance (CL)	50 pF
Logic integrated circuit type	AND-OR-INVERT GATE
MaximumI(ol)	0.006 A
Number of functions	2
Number of entries	6
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2/6 V
Prop。Delay @ Nom-Sup	20 ns
propagation delay (tpd)	190 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	1.4 V
Nominal supply voltage (Vsup)	2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

This Material Copyrighted By Its Respective Manufacturer

	MN74HC51S	MN74HC51
Description	AND-OR-Invert Gate, HC/UH Series, 2-Func, 6-Input, CMOS, PDSO14, SOP-14	AND-OR-Invert Gate, HC/UH Series, 2-Func, 6-Input, CMOS, PDIP14, PLASTIC, DIP-14
Is it Rohs certified?	incompatible	incompatible
Parts packaging code	SOIC	DIP
package instruction	SOP-14	PLASTIC, DIP-14
Contacts	14	14
Reach Compliance Code	unknown	unknown
series	HC/UH	HC/UH
JESD-30 code	R-PDSO-G14	R-PDIP-T14
JESD-609 code	e0	e0
Load capacitance (CL)	50 pF	50 pF
Logic integrated circuit type	AND-OR-INVERT GATE	AND-OR-INVERT GATE
MaximumI(ol)	0.006 A	0.006 A
Number of functions	2	2
Number of entries	6	6
Number of terminals	14	14
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	DIP
Encapsulate equivalent code	SOP14,.25	DIP14,.3
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
power supply	2/6 V	2/6 V
Prop。Delay @ Nom-Sup	20 ns	20 ns
propagation delay (tpd)	190 ns	190 ns
Certification status	Not Qualified	Not Qualified
Schmitt trigger	NO	NO
Maximum supply voltage (Vsup)	6 V	6 V
Minimum supply voltage (Vsup)	1.4 V	1.4 V
Nominal supply voltage (Vsup)	2 V	2 V
surface mount	YES	NO
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED

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