SP8400KGMPES datasheet, PDF - EEWORLD Datasheet

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SP8400KGMPES: DescriptionPrescaler, 1-Func, Bipolar, PDSO28, PLASTIC, SO-28; Categorylogic logic; File Size113KB，6 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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SP8400KGMPES Overview

Prescaler, 1-Func, Bipolar, PDSO28, PLASTIC, SO-28

SP8400KGMPES Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Microsemi
Parts packaging code	SOIC
package instruction	SOP, SOP28,.4
Contacts	28
Reach Compliance Code	unknown
JESD-30 code	R-PDSO-G28
JESD-609 code	e0
Logic integrated circuit type	PRESCALER
Number of data/clock inputs	1
Number of functions	1
Number of terminals	28
Maximum operating temperature	75 °C
Minimum operating temperature	-10 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP28,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	152 mA
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	BIPOLAR
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
minfmax	1500 MHz

SP8400KGMPES Preview

SP8400

Very Low Phase Noise Synthesiser Divider

DS3739 - 2.1 April 1994

The SP8400 is a very low phase noise programmable

divider which is based on a divide by 8/9 dual modulus

prescaler and a 12 stage control counter. This gives a minimum

division ratio of 56 (64 for fractional - N synthesis applications),

and a maximum division ratio of 4103. Special circuit

techniques have been used to reduce the phase noise

considerably below that produced by standard dividers.The

data inputs are CMOS or TTL compatible.

The SP8400 is packaged in a 28 pin plastic SO package.

+5V

GND

CLOCK INPUT

GND

+5V

GND

N/C

OUTPUT

N/C

+5V

N/C

FEATURES

Very low Phase Noise (Typically -156dBc/Hz at 1kHz

offset)

Supply Voltage 5V

ABSOLUTE MAXIMUM RATINGS

Supply Voltage

Output Current

Storage Temperature Range

Maximum Clock Input Voltage

6.5V

20mA

-55°C to +125°C

2.5V p-p

MP28

Fig.1 Pin connections - top view

ORDERING INFORMATION

SP8400 KG MPES(Commercial Grade)

–10

–20

–30

–40

–50

(f) (dBc/Hz) –3dB

–60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

100

Frequency (Hz)

10k

100k

Fig.2 Typical single sideband phase noise measured at 300MHz

SP8400

ELECTRICAL CHARACTERISTICS

Guaranteed over: Supply voltage V

= +4.75V to +5.25V Temperature T

amb

= -10°C to +75°C

Tested at +4.75V and +5.25V at T

amb

= +25°C

Characteristic

Supply current

Output voltage swing

Input sensitivity 200MHz to 1.5GHz

Min.

4, 11, 12, 18

20, 21

7, 8

122

320

Value

Typ. Max.

137

410

152

dBm

Output loaded with 300R See Fig.4

p-p @ 1.5GHz input

71 mode

See Fig.4

RMS Sine wave into 50 Ohms

(dBm equivalent) See Fig.3

Units

Conditions

140

(-4)

Data Inputs

Logic high voltage

Low low voltage

Input current

2.2

0.8

180

µA

5V Data input voltage

600

500

400

mV rms

355mV

300

OPERATING WINDOW

200

140mV

100

200

400

600

800

1000

1200

1400

1600

FREQUENCY MHz

Fig.3 Typical input sensitivity

SP8400

TTL/CMOS

MODULUS

CONTROL

1nF

50R

SIGNAL

GENERATOR

SP8400

OUTPUT

220nF

TTL/CMOS

MODULUS

CONTROL

1nF

10nF

1nF

2x330R

10nF

50R

Fig.4 Test circuit

APPLICATIONS INFORMATION

Circuit description, synthesiser divider

The divider is based on a divide by 8/9 modulus prescaler,

and a 12 stage control counter. This gives minimum fractional

– N division ratio of 64 (56 for general division), and a maximum

division ratio of 4103. The inputs to the control counter are TTL/

CMOS compatible. There is a fixed offset of 8 between the

number on the data lines and the actual division ratio.

The output is one transition only per divide cycle. This

eliminates the problem of where to put the redundant edge

when the divider is used in a fractional–N system, and also

avoids the problem of how to define the output pulse width. This

means that the overall division ratio conventionally defined in

terms of the rate of edges of the same polarity is twice the

selected division ratio.

Equations for division

The M and A data inputs form a 12 bit number with A0

being the least significant bit and M8 being the most significant

bit.

Definition 1:

Division ratio – (input frequency to output

edges, positive or negative).

= Number loaded + 8

Definition 2:

Division ratio – (input frequency to output

frequency).

= (Number loaded + 8) x 2

SP8400

Available division ratio

All division ratios of 64 to 4103 (Definition 1) will return the

divider to the same internal state at the end of the count and

hence these are the only divisional ratios to be used for

fractional–N synthesiser application.

All division ratios of 56 to 4103 are available for general division

purposes. Additional division ratios available for general

division are:-

8,9

16, 17, 18

24, 25, 26, 27

32, 33, 34, 35, 36

40, 41, 42, 43, 44, 45

48, 49, 50, 51, 52, 53, 54

+5V

INPUTS

+15V

2 x BF569

(or similar)

1nF

CLOCK INPUT

50R

SP8400

10nF

INPUTS

330R

1nF

10nF

1nF

2x330R

10nF

Fig.5 Typical application combining output to increase signal and retain low phase noise

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