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CU41AF-FREQ1

Description
TTL Output Clock Oscillator, 0.01MHz Min, 69.999MHz Max, FULL SIZE, DIP-4
CategoryPassive components    oscillator   
File Size103KB,1 Pages
ManufacturerCal Crystal Lab Inc / Comclok Inc
Websitehttps://www.transko.com
Download Datasheet Parametric View All

CU41AF-FREQ1 Overview

TTL Output Clock Oscillator, 0.01MHz Min, 69.999MHz Max, FULL SIZE, DIP-4

CU41AF-FREQ1 Parametric

Parameter NameAttribute value
MakerCal Crystal Lab Inc / Comclok Inc
Reach Compliance Codecompliant
maximum descent time10 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
Installation featuresTHROUGH HOLE MOUNT
Maximum operating frequency69.999 MHz
Minimum operating frequency0.01 MHz
Maximum operating temperature70 °C
Minimum operating temperature
Oscillator typeTTL
Output load10 TTL
physical size20.83mm x 13.21mm x 6.48mm
longest rise time10 ns
Nominal supply voltage5 V
surface mountNO
maximum symmetry60/40 %
Cal Crystal Lab, Inc. / Comclok, Inc. 800-333-9825
1156 North Gilbert Street • Anaheim, CA 92801
TRI-STATE TTL CLOCK OSCILLATORS
(FULL & HALF SIZE)
MODEL CU
5.0VDC
Model
Frequency Range
Frequency Stability
Operating Temperature Range
Storage Temperature Range
Current Consumption
Supply Voltage
Symmetry
Rise & Fall Time (Tr & Tf)
Logic “1”
Logic “0”
Output Load
Aging
Enable Input
10kHz ~ 69.999MHz
100ppm Standard, Optional Tolerances Available
0
o
C ~+70
o
C, Extended Temperature Ranges Available
-55
o
C ~+125
o
C
10.0KHz ~ 23.999MHz:
15mA Max.
24.000MHz ~ 69.999MHz: 30mA Max.
+5 VDC
±
10%
60/40 @ 50% Vcc, Optional Tolerances Available
10 nSec Max
2.8 VDC Min
0.4 VDC Max
10TTL
< 5ppm per year
Enable - Logic “1” 2.0 VDC Min
Disable - Logic “0” 0.5 VDC Max.
CU
70MHz ~ 160.0MHz
CU
100ppm Standard, Optional Tolerances Available
0
o
C ~+70
o
C, Extended Temperature Ranges Available
-55
o
C ~+125
o
C
70.0MHz ~ 99.9MHz:
30mA Max.
100.00MHz ~ 129.9MHz: 35mA Max.
130.00MHz ~ 160.00MHz: 40mA Max.
+5 VDC
±
10%
60/40 @ 50% Vcc, Optional Tolerances Available
4 nSec Max
2.8 VDC Min
0.4 VDC Max
2TTL Other Loads Available
< 5ppm per year
Enable - Logic “1” 2.0 VDC Min
Disable - Logic “0” 0.5 VDC Max.
FULL SIZE TRI-STATE TTL
PINS
1
7
8
14
TEST CIRCUIT FULL SIZE
CONNECTIONS
ENABLE / DISABLE
GND
OUTPUT
+5 VDC
±10%
HALF SIZE TRI-STATE TTL
PINS
1
4
5
8
CONNECTIONS
ENABLE / DISABLE
GND
OUTPUT
+5 VDC
±10%
TEST CIRCUIT HALF SIZE
NOTE:
1. C
L
Capacitance includes probe and test jig (15pF typical)
2. R
L
= 400Ω - 10 TTL
2KΩ - 10 LSTTL
3. All diodes are 1N941, 1N43064 or equivalent
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