P4C1282-20PM datasheet, PDF - EEWORLD Datasheet

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P4C1282-20PM: DescriptionStandard SRAM, 64KX4, 20ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28; Categorystorage storage; File Size862KB，11 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P4C1282-20PM Overview

Standard SRAM, 64KX4, 20ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28

P4C1282-20PM Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Pyramid Semiconductor Corporation
Parts packaging code	DIP
package instruction	0.300 INCH, PLASTIC, DIP-28
Contacts	28
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Maximum access time	20 ns
JESD-30 code	R-PDIP-T28
JESD-609 code	e0
length	34.861 mm
memory density	262144 bit
Memory IC Type	STANDARD SRAM
memory width	4
Number of functions	1
Number of terminals	28
word count	65536 words
character code	64000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	64KX4
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	5.334 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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P4C1281/P4C1282

ULTRA HIGH SPEED 64K X 4

cmoS STATIc RAmS

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)

– 12/15/20/25 ns (Commercial)

– 15/20/25/35 ns (Industrial)

– 20/25/35/45 ns (Military)

Low Power Operation

5V ± 10% Power Supply

Separate Inputs and Outputs

– P4C1281 Input Data at Outputs during Write

– P4C1282 Outputs in High Z during Write

Fully TTL Compatible Inputs and Outputs

Standard Pinout (JEDEC Approved)

– 28-Pin 300 mil DIP, SOJ

– 28-Pin 350 x 550 mil LCC

DESCRIPTIOn

The P4C1281 and P4C1282 are 262,144-bit (64Kx4) ultra

high-speed static RAMs similar to the P4C1258, but with

separate data I/O pins. The P4C1281 features a transpar-

ent write operation; the outputs of the P4C1282 are in high

impedance during the write cycle. The RAMs operate from

a single 5V ± 10% tolerance power supply.

Access times as fast as 12 nanoseconds are available,

permitting greatly enhanced system operating speeds.

CMOS is used to reduce power consumption.

The P4C1281 and P4C1282 are available in 28-pin 300

mil DIP and SOJ, and a 28-pin 350x550 mil LCC providing

excellent board level densities.

FUnCTIOnAL BLOCk DIAgRAM

PIn COnFIgURATIOnS

DIP (P5, C5, D5-2), SOJ (J5)

LCC (L5)

Document #

SRAM136

REV OR

Revised July 2009

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