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PDM31548SA15TITR

Description
Standard SRAM, 256KX8, 15ns, CMOS, PDSO44
Categorystorage    storage   
File Size350KB,9 Pages
ManufacturerParadigm Technology Inc
Download Datasheet Parametric View All

PDM31548SA15TITR Overview

Standard SRAM, 256KX8, 15ns, CMOS, PDSO44

PDM31548SA15TITR Parametric

Parameter NameAttribute value
MakerParadigm Technology Inc
package instruction,
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time15 ns
JESD-30 codeR-PDSO-G44
memory density2097152 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of ports1
Number of terminals44
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX8
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal locationDUAL
PRELIMINARY
PDM31548
PDM31548
128K x 16 CMOS
3.3V Static RAM
1
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7
Features
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Description
The PDM31548 is a high-performance CMOS static
RAM organized as 131,072 x 16 bits. The PDM31548
features low power dissipation using chip enable
(CE) and has an output enable input (OE) for fast
memory access. Byte access is supported by upper
and lower byte controls.
The PDM31548 operates from a single 3.3V power
supply and all inputs and outputs are fully TTL-
compatible.
The PDM31548 is available in a 44-pin 400-mil plas-
tic SOJ and a plastic TSOP (II) package for high-
density surface assembly and is suitable for use in
high-speed applications requiring high-speed
storage.
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High-speed access times
- Com’l: 10, 12, 15 and 20 ns
- Ind: 12, 15 and 20 ns
Low power operation (typical)
- PDM31548SA
Active: 250 mW
Standby: 25 mW
High-density 128K x 16 architecture
3.3V (±0.3V) power supply
Fully static operation
TTL-compatible inputs and outputs
Output buffer controls: OE
Data byte controls: LB, UB
Packages:
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
Functional Block Diagram
Row Address
Buffer
Row Decoder
Vcc
Vss
A8-A0
Memory
Cell
Array
256 x
x
128 x 32
512 128 x 32
8
9
10
11
I/O15-I/O0
Data
Input/
Output
Buffer
Sense Amp
Column
Decoder
WE
OE
UB
LB
CE
Control
Logic
Clock
Generator
Column
Address
Buffer
12
A16 - A9
A15-A9
Rev. 1.3 - 4/13/98
1
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