P4C187/P4C187L
ULTRA HIGH SPEED 64K x 1
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35/45 ns (Commercial)
– 12/15/20/25/35 /45 ns (Industrial)
– 15/20/25/35/45/55/70/85 ns (Military)
Low Power Operation
Single 5V±10% Power Supply
Data Retention with 2.0V Supply (P4C187L)
Separate Data I/O
Three-State Output
TTL Compatible Output
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 22-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 22-Pin 290x490 mil LCC
– 28-Pin 350x550 mil LCC
DESCRIPTIOn
The P4C187/P4C187L are 65, 536-bit ultra high speed static
RAMs organized as 64K x 1. The CMOS memories require
no clocks or refreshing and have equal access and cycle
times. The RAMs operate from a single 5V ± 10% toler-
ance power supply. Data integrity is maintained for supply
voltages down to 2.0V for the Low Power version, typically
drawing 10µA.
Access times as fast as 10 nanoseconds are available,
greatly enhancing system speeds. CMOS reduces power
consumption to a low 743mW active, 193/83mW standby
for TTL/CMOS inputs and only 5.5 mW standby for the
P4C187L.
The P4C187/P4C187L are available in 22-pin 300 mil DIP,
24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages pro-
viding excellent board level densities.
FUnCTIOnAL BLOCk DIAgRAM
PIn COnFIgURATIOnS
DIP (P3, D3, C3)
SOJ (J4)
LCC configurations at end of datasheet
Document #
SRAM111
REV D
Revised October 2013
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
MAxIMUM RATIngS
(1)
Sym
V
CC
V
TERM
T
A
T
BIAS
T
STG
P
T
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
7.0V)
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-55 to +125
-55 to +125
-65 to +150
1.0
Unit
V
V
°C
°C
°C
W
RECOMMEnDED OPERATIng COnDITIOnS
grade
(2)
Commercial
Industrial
Military
Ambient Temp
0°C to 70°C
-40°C to +85°C
-55°C to +125°C
gnD
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITAnCES
(4)
Sym
C
IN
C
OUT
Parameter
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Conditions
V
IN
=0V
V
OUT
=0V
Typ
5
7
Unit
pF
pF
Input Capacitance
Output Capacitance
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Test Conditions
P4C187
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
-1.2
0.4
2.4
MIL
IND/COM
MIL
IND/COM
MIL
IND/COM
MIL
IND/COM
P4C187L
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
-1.2
0.4
2.4
Unit
V
V
V
V
V
V
V
Input Clamp Diode Voltage V
CC
= Min, I
IN
= 18 mA
Output Low Voltage (TTL
Load)
Output High Voltage (TTL
Load)
Input Leakage Current
I
OL
= +8 mA, V
CC
= Min
I
OH
= -4 mA, V
CC
= Min
V
CC
= Max,
V
IN
= GND to V
CC
-10
-5
-10
-5
—
—
—
—
+10
+5
+10
+5
40
35
20
15
-5
N/A
-5
N/A
—
—
—
—
+5
µA
N/A
+5
µA
N/A
40
mA
N/A
1.0
mA
N/A
I
LI
I
LO
Output Leakage Current
V
CC
= Max,
CE
= V
IH
,
V
OUT
= GND to V
CC
I
SB
Standby Power Supply
Current (TTL Input Levels)
CE
≥ V
IH
, V
CC
= Max, f = Max,
Outputs Open
CE
≥ V
HC
, V
CC
= Max, f = 0,
Outputs Open
V
IN
≤ V
LC
or V
IN
≥ V
HC
I
SB1
Standby Power Supply
Current (CMOS Input
Levels)
N/A = Not applicable
notes:
1. Stresses greater than those listed under MAxIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAxIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Document #
SRAM111
REV D
Page 2
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
POWER DISSIPATIOn CHARACTERISTICS VS. SPEED
Sym
I
CC
Parameter
Dynamic
Operating
Current*
Temperature Range
Commercial
Industrial
Military
-10
180
N/A
N/A
-12
170
180
N/A
-15
160
170
170
-20
155
160
160
-25
150
155
155
-35
N/A
150
150
-45
N/A
N/A
145
-55
N/A
N/A
145
-70
N/A
N/A
145
-85
N/A
N/A
145
Unit
mA
mA
mA
* V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
.
DATA RETEnTIOn CHARACTERISTICS (P4C187L Military Temperature Only)
Sym
V
DR
I
CCDR
t
CDR
t
R†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
CE
≥ V
CC
-0.2V,
V
IN
≥ V
CC
-0.2V
or V
IN
≤ 0.2V
0
t
RC§
Test Conditions
Min
2.0
10
15
600
900
Typ* V
CC
=
2.0V
3.0V
Max V
CC
=
2.0V
3.0V
Unit
V
µA
ns
ns
* T
A
= +25°C
§ t
RC
= Read Cycle Time
† This Parameter is guaranteed but not tested
DATA RETEnTIOn WAVEFORM
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
PU
t
PD
Parameter
Read Cycle
Time
Address Access
Time
Chip Enable
Access Time
Output Hold
from Address
Change
Chip Enable to
Output in Low Z
Chip Disable
to Output in
High Z
Chip Enable to
Power Up Time
Chip Disable to
Power Down
0
10
2
2
5
0
12
-10
-12
-15
-20
-25
-35
-45
-55
-70
-85
Unit
ns
85
85
2
2
30
0
55
70
0
85
35
ns
ns
ns
ns
ns
ns
ns
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
10
10
10
2
2
6
0
15
12
12
12
2
2
8
0
20
15
15
15
2
2
10
0
25
20
20
20
2
2
12
0
35
25
25
25
2
2
17
0
45
35
35
35
2
2
20
0
45
45
45
2
2
25
55
55
55
2
2
70
70
70
85
Document #SRAM111 REV D
Page 3
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
TIMIng WAVEFORM OF READ CYCLE nO. 1
(5)
TIMIng WAVEFORM OF READ CYCLE nO. 2
(6)
notes:
5.
CE
is LOW and
WE
is HIGH for READ cycle.
6.
WE is
HIGH,
and address must be valid prior to or coincident with CE
transition
LOW.
7. Transition is measured ± 200 mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM111
REV D
Page 4
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
Parameter
Write Cycle
Time
Chip Enable
Time to End of
Write
Address Valid
to End of Wrtite
Address Set-up
Time
Write Pulse
Width
Address Hold
Time from End
of Write
Data Valid to
End of Write
Data Hold Time
Write Enable
to Output in
High Z
Output Active
from End of
Write
0
-10
-12
-15
-20
-25
-35
-45
-55
-70
-85
Unit
ns
ns
ns
ns
ns
ns
ns
ns
35
ns
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
10
8
8
0
8
0
6
0
6
12
10
10
0
10
0
7
0
7
15
12
12
0
12
0
10
0
8
20
15
15
0
15
0
13
0
12
25
20
20
0
20
0
15
0
15
35
25
25
0
25
0
20
0
17
45
30
30
0
30
0
25
0
20
55
35
35
0
35
0
30
0
25
70
40
40
0
40
0
35
0
30
85
45
45
0
40
0
40
0
t
OW
0
0
0
0
0
0
0
0
0
ns
TIMIng WAVEFORM OF WRITE CYCLE nO. 1 (WE COnTROLLED)
(9)
notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
Document #SRAM111 REV D
Page 5
Linux and Android
京公网安备 11010802033920号
EEWORLD
