P4C187L-20LI datasheet, PDF - EEWORLD Datasheet

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P4C187L-20LI: DescriptionStandard SRAM, 64KX1, 20ns, CMOS, 0.290 X 0.490 INCH, LCC-18; Categorystorage storage; File Size978KB，12 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P4C187L-20LI Overview

Standard SRAM, 64KX1, 20ns, CMOS, 0.290 X 0.490 INCH, LCC-18

P4C187L-20LI Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Pyramid Semiconductor Corporation
Parts packaging code	LCC
package instruction	0.290 X 0.490 INCH, LCC-18
Contacts	18
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	20 ns
JESD-30 code	R-XQCC-N22
length	12.466 mm
memory density	65536 bit
Memory IC Type	STANDARD SRAM
memory width	1
Number of functions	1
Number of terminals	22
word count	65536 words
character code	64000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64KX1
Package body material	UNSPECIFIED
encapsulated code	QCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	2.032 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.366 mm

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P4C187/P4C187L

ULTRA HIGH SPEED 64K x 1

STATIC CMOS RAMS

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)

– 10/12/15/20/25/35/45 ns (Commercial)

– 12/15/20/25/35 /45 ns (Industrial)

– 15/20/25/35/45/55/70/85 ns (Military)

Low Power Operation

Single 5V±10% Power Supply

Data Retention with 2.0V Supply (P4C187L)

Separate Data I/O

Three-State Output

TTL Compatible Output

Fully TTL Compatible Inputs

Standard Pinout (JEDEC Approved)

– 22-Pin 300 mil DIP

– 24-Pin 300 mil SOJ

– 22-Pin 290x490 mil LCC

– 28-Pin 350x550 mil LCC

DESCRIPTIOn

The P4C187/P4C187L are 65, 536-bit ultra high speed static

RAMs organized as 64K x 1. The CMOS memories require

no clocks or refreshing and have equal access and cycle

times. The RAMs operate from a single 5V ± 10% toler-

ance power supply. Data integrity is maintained for supply

voltages down to 2.0V for the Low Power version, typically

drawing 10µA.

Access times as fast as 10 nanoseconds are available,

greatly enhancing system speeds. CMOS reduces power

consumption to a low 743mW active, 193/83mW standby

for TTL/CMOS inputs and only 5.5 mW standby for the

P4C187L.

The P4C187/P4C187L are available in 22-pin 300 mil DIP,

24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages pro-

viding excellent board level densities.

FUnCTIOnAL BLOCk DIAgRAM

PIn COnFIgURATIOnS

DIP (P3, D3, C3)

SOJ (J4)

LCC configurations at end of datasheet

Document #

SRAM111

REV D

Revised October 2013

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