EEWORLDEEWORLDEEWORLD

Part Number

Search

PDM41256SA10SOI

Description
Standard SRAM, 32KX8, 10ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
Categorystorage    storage   
File Size283KB,8 Pages
ManufacturerIXYS
Environmental Compliance  
Download Datasheet Parametric View All

PDM41256SA10SOI Overview

Standard SRAM, 32KX8, 10ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28

PDM41256SA10SOI Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?incompatible
MakerIXYS
Parts packaging codeSOJ
package instruction0.300 INCH, PLASTIC, SOJ-28
Contacts28
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum access time10 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-J28
JESD-609 codee0
length18.415 mm
memory density262144 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals28
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ28,.34
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height3.75 mm
Maximum standby current0.02 A
Minimum standby current4.5 V
Maximum slew rate0.2 mA
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
PDM41256
256K Static RAM
32K x 8-Bit
Features
n
1
2
3
4
5
6
7
Description
The PDM41256 is a high-performance CMOS static
RAM organized as 32,768 x 8 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE) inputs are both LOW.
Reading is accomplished when WE remains HIGH
and CE and OE are both LOW.
The PDM41256 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41256 comes in two versions:
the standard power version PDM41256SA and the
low power version PDM41256LA. Both versions are
functionally the same and differ only in their power
consumption.
The PDM41256 is available in a 28-pin plastic TSOP
(I) and a 28-pin 300-mil plastic SOJ.
n
High-speed access times
Com’l: 7, 8, 10, 12 and 15ns
Ind’l: 8, 10, 12 and 15ns
(use 15ns for slower designs)
Low power operation (typical)
- PDM41256SA
Active: 475 mW
Standby: 100 mW
- PDM41256LA
Active: 425mW
Standby: 25 mW
Single +5V (±10%) power supply
TTL-compatible inputs and outputs
Packages
Plastic SOJ (300 mil) - SO
Plastic TSOP (I) - T
n
n
n
Functional Block Diagram
A
0
A
14
Decoder
Memory
Matrix
Addresses
8
9
10
I/O
0
I/O
7
• • • • •
Input
Data
Control
Column I/O
11
12
1
CE
WE
OE
Rev. 4.4 - 4/29/98
How to Generate Random Arrays in DSP 2812
2812 eCAN module ECanaMboxes.MBOX5.MDRL.all = 0x01234567; ECanaMboxes.MBOX5.MDRH.all = 0x89ABCDEF; Send data through mailbox No. 5 I now want to use mailbox No. 5 to send some random arrays. How to wr...
tangwenwenit Embedded System
Ave simple question, please help me urgently!!!!!!!!!!!!!!!!!!
#include#includevoid delay(unsigned int ms) {unsigned int temp;for(temp=0;temp First of all, the maximum value of "delay(100000);" unsigned int type variable cannot exceed 65535, 100000 has overflowed...
zm19400916 Microchip MCU
Five major problems of smart home to be solved
[color=#333333][Guide] This article is provided by Scan IC Network Platform. Smart homes, which have attracted much attention in Silicon Valley in the past few years, have shown signs of falling out o...
扫IC网`Allen Integrated technical exchanges
Teacher Guo Tianxiang C51 video seed collection
Teacher Guo Tianxiang’s C51 video seed collection, feels good!...
baijin0002 51mcu
ISP1504 ULPI transceiver sometimes fails to write reg~
Please help, at startup the debugging information appears HCD driver DLL attach EHCD!HCD_Init ISP1504_WriteReg: ############ Error -- failed to write ULPI reg 5 OTG reset ISP1504_WriteReg: ###########...
snpty Embedded System
【Little fresh meat!】Introduction to Altera 14 nm Stratix 10 FPGA and SoC--EEWORLD University
Altera 14 nm Stratix 10 FPGA and SoC Introduction : https://training.eeworld.com.cn/course/606[size=4]Stratix 10 FPGAs and SoCs use Altera's revolutionary HyperFlex FPGA architecture, manufactured usi...
chenyy FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 955  1898  1309  336  2928  20  39  27  7  59 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号