PRELIMINARY
PDM41034
1 Megabit Static RAM
128K x 8-Bit
Revolutionary Pinout
Features
s
High speed access times
Com’l: 10, 12, 15, 17 and 20 ns
Ind’l.: 12, 15, 17 and 20 ns
s
Low power operation
- PDM41034SA
Active: 400 mW (typ.)
Standby: 150 mW (typ.)
- PDM41034LA
Active: 350 mW (typ.)
Standby: 100 mW (typ.)
s
Single +5V (±10%) power supply
s
TTL-compatible inputs and outputs
s
Packages
Plastic SOJ (300 mil) - TSO
Plastic SOJ (400 mil) - SO
Plastic TSOP - T
Description
The PDM41034 is a high-performance CMOS static
RAM organized as 131,072 x 8 bits. This product is
produced in Paradigm’s proprietary CMOS
technology which offers the designer the highest
speed parts. Writing is accomplished when the write
enable (WE) and the chip enable (CE) inputs are
both LOW. Reading is accomplished when WE
remains HIGH and CE and OE are both LOW.
The PDM41034 operates from a single +5.0V power
supply and all the inputs and outputs are fully TTL
compatible. The PDM41034 comes in two versions,
the standard power version PDM41034SA and a low
power version the PDM41034LA. The two versions
are functionally the same and only differ in their
power consumption.
The PDM41034 is available in a 32-pin plastic TSOP,
300-mil and 400-mil plastic SOJ.
1
2
3
4
5
6
7
8
9
10
11
12
Functional Block Diagram
Rev. 2.0 - 7/17/96
4-33
PRELIMINARY
PDM41034
SOJ
Pin Configuration
TSOP
Pin Description
Name
A16-A0
I/O7-I/O0
OE
WE
CE
V
CC
V
SS
Description
Address Inputs
Data Inputs/Outputs
Output Enable Input
Write Enable Input
Chip Enable Input
Power (+5V)
Ground
OE
X
L
X
H
WE
X
H
L
H
CE
H
L
L
L
I/O
Hi-Z
D
OUT
D
IN
Hi-Z
MODE
Standby
Read
Write
Output Disable
Truth Table
(1)
NOTE: 1. H = V
IH
, L = V
IL
, X = DON’T CARE
Absolute Maximum Ratings
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with Respect to V
SS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Com’l.
–0.5 to +7.0
–55 to +125
–55 to +125
1.0
50
Ind.
–0.5 to +7.0
–65 to +135
–65 to +150
1.0
50
Unit
V
°C
°C
W
mA
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RA
TINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions
Symbol
V
CC
V
SS
Industrial
Commercial
Parameter
Supply Voltage
Supply Voltage
Ambient Temperature
Ambient Temperature
Min.
4.5
0
–40
0
Typ.
5.0
0
25
25
Max.
5.5
0
85
70
Unit
V
V
°C
°C
4-34
Rev. 2.0 - 7/17/96
PRELIMINARY
PDM41034
DC Electrical Characteristics
(V
CC
= 5.0V ± 10%)
PDM41034SA
Symbol
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 8 mA, V
CC
= Min.
I
OL
= 10 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
Test Conditions
V
CC
= MAX., V
IN
= V
SS
to V
CC
V
CC
= MAX.,
CE = V
IH
, V
OUT
= V
SS
to V
CC
Com’l/
Ind.
Com’l/
Ind.
Min.
–5
–5
–0.5
(1)
2.2
—
—
2.4
Max.
5
5
0.8
6.0
0.4
0.5
—
PDM41034LA
Min.
–5
–5
–0.5
(1)
2.2
—
—
2.4
Max.
5
5
0.8
6.0
0.4
0.5
—
Unit
µA
µA
V
V
V
V
V
1
2
3
4
NOTE: 1. V
IL
(min) = –3.0V for pulse width less than 20 ns
Power Supply Characteristics
-10
Symbol Parameter
I
CC
Operating Current
CE = V
IL
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
SB1
Full Standby Current
CE
≥
V
HC
f=0
V
CC
= Max.,
V
IN
≥
V
CC
– 0.2V or
≤
0.2V
-12
-15
-17
-20
Unit
mA
mA
Power Com’l. Com’l Ind. Com’l Ind. Com’l Ind. Com’l Ind.
SA
250
230
240
185
195
165
175
155
165
LA
230
210
220
165
175
155
165
140
150
5
6
7
8
9
SA
LA
SA
LA
80
75
20
10
70
65
20
10
70
65
25
10
55
50
10
5
55
50
15
10
50
45
10
5
50
45
15
10
45
40
10
5
45
40
15
10
mA
mA
mA
mA
NOTES: All values are maximum guaranteed values.
V
LC
≤
0.2V, V
HC
≥
V
CC
– 0.2V
Capacitance
(1)
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Max.
8
8
Unit
pF
pF
10
11
12
NOTE:1. This parameter is determined by device characterization but is not production tested.
Rev. 2.0 - 7/17/96
4-35
PRELIMINARY
PDM41034
AC Test Conditions
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
V
SS
to 3.0V
3 ns
1.5V
1.5V
See Figures 1 and 2
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
, t
LZOE
,
t
HZOE
)
Figure 3.
4-36
Rev. 2.0 - 7/17/96
PRELIMINARY
PDM41034
Read Cycle No. 1
(4, 5)
1
2
Read Cycle No. 2
(2, 4, 6)
3
4
5
6
AC Electrical Characteristics
Description
READ Cycle
READ cycle time
Address access time
Chip enable access time
Output hold from address change
Chip enable to output in low Z
(1,3)
Chip disable to output in high Z
(1,2,3)
Chip enable to power up time
(3)
Chip disable to power down time
(3)
Output enable access time
Output enable to output in low Z
(1,3)
Output disable to output in high Z
(1,3)
Sym
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
0
6
0
10
6
0
6
3
5
6
0
12
6
0
6
-10
(7)
-12
(7)
-15
-17
-20
7
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
10
10
10
3
5
6
0
15
6
0
6
12
12
12
3
5
7
0
17
6
0
6
15
15
15
3
5
7
0
20
6
17
17
17
3
5
8
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
9
10
11
12
Notes referenced are after Data Retention Table.
Rev. 2.0 - 7/17/96
4-37
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