512 K x 32 Static RAM
PUMA 68SV16000XB - 012/015/017
Issue 5.2 April 2001
Description
The PUMA68 range of devices provide a high
density surface mount industry standard memory
solution which may accommodate various memory
technologies including SRAM, EEPROM and
Flash. The devices are designed to offer a defined
upgrade path and may be user configured as 8, 16
or 32 bits wide.
The PUMA68SV16000XB is a 512Kx32 SRAM mod-
ule housed in a 68 Jleaded package which complies
with the JEDEC 68 PLCC standard. Access times of
12, 15 or 17ns are available. The 3.3V low voltage
device is available to commercial and industrial
temperature grade.
Block Diagram
A0~A18
/OE
/WE
512K x 8
SRAM
/CS1
/CS2
/CS3
/CS4
D0~7
D8~15
D16~23
D24~31
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
Features
• Access times of 12/15/17 ns.
• 3.3V + 10%.
• Commercial and Industrial temperature grades
• JEDEC standard 68 J Lead footprint.
• Industry standard pinout.
• May be organised as 512K x 32, 1M x 16, 2M X 8
• Operating Power
(32 Bit) 2.74W (max)
• Low power standby.
(TTL) 0.87W (max)
(CMOS) 145mW (max)
• Completely Static Operation.
Pin Definition
See page 2.
Pin Functions
Description
Address Input
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power
Ground
Signal
A0~A18
D0~D31
/CS1~4
/WE
/OE
NC
V
CC
V
SS
Package Details
PUMA 68 - Plastic 68 ‘J’ Leaded Package
Max. Dimensions (mm) - 25.27 x 25.27 x 5.08
Elm Road, West Chirton Industrial Estate, North Shields, NE29 8SE, England.
TEL +44 (0191) 2930500. FAX +44 (0191) 2590997 E-mail:
hmpsales@mosaicsemi.com
Pin Definition - PUMA68SV16000X
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal
V
CC
NC
/CS1
/CS2
/CS3
/CS4
A17
A18
D16
D17
D18
D19
V
SS
D20
D21
D22
D23
V
CC
D24
D25
D26
D27
V
SS
D28
D29
D30
D31
A6
A5
A4
A3
A2
A1
A0
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal
V
CC
A13
A12
A11
A10
A9
A8
A7
D0
D1
D2
D3
V
SS
D4
D5
D6
D7
V
CC
D8
D9
D10
D11
V
SS
D12
D13
D14
D15
A14
A15
A16
/WE
/OE
NC
NC
PAGE 2
Issue 5.2 April 2001
Absolute Maximum Ratings
(1)
DC Operating Conditions
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Symbol
V
T
P
T
T
STG
Min
-0.3
to
4.0
-55
to
Max
+4.6
Unit
V
W
+125
O
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
Notes : (1) Pulse Width : -2.0V for less than 10ns.
(1)
Min
3.0
2.0
-0.3
0
-40
Typ
3.3
-
-
-
-
Max
3.6
V
CC
+0.3
0.8
70
85
Unit
V
V
V
O
O
C
C
(I Suffix)
DC Electrical Characteristics
(V
CC
=3.3V+10%, T
A
=-40
O
C to +85
O
C)
Parameter
Input Leakage Current
Output Leakage Current
Average Supply Current
(2)
Symbol Test Condition
I
LI
I
LO
32 Bit
16 Bit
8 Bit
I
CC32
I
CC16
I
CC8
I
SB
I
SB1
V
OL
V
OH
V
IN
=0V to V
CC
V
I/O
=0V to V
CC
/CS =V
IL
, I
I/O
=0mA,f=f
max
As Above.
As Above.
/CS =V
IH
,Min Cycle
/CS
>
V
CC
-0.2V, 0.2V
>V
IN
>
V
CC
-0.2V, f=0
I
OL
=8.0mA, V
CC
=Min
I
OH
=-4.0mA, V
CC
=Min
(1)
(1)
Min
-8
-8
-
-
-
-
-
-
2.4
Typ
-
-
-
-
-
-
-
-
-
Max
8
8
760
490
370
240
40
0.4
-
Unit
µ
A
µ
A
mA
mA
mA
mA
mA
V
V
Standby Supply Current
TTL
CMOS
Output Voltage Low
Output Voltage High
Notes
(1) /CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
(2) At f=f
MAX
address and data inputs are cycling at max frequency.
PAGE 3
Issue 5.2 April 2001
Capacitance
(V
CC
= 3.3V, T
A
= 25
O
C, F=1MHz.)
Parameter
Input Capacitance,
Address, /OE, /WE
Output Capacitance,
8 bit mode (worst case)
Note : These Parameters are calculated not measured.
Symbol
C
IN1
C
I/O
Test Condition
V
IN
=0V
V
I/O
=0V
Min
-
-
Typ
-
-
Max
30
34
Unit
pF
pF
Test Conditions
•
•
•
•
•
•
Input pulse levels : 0V to 3.0V
Input rise and fall times : 3ns
Input and Output timing reference levels : 1.5V
Output Load : See Load Diagram.
V
CC
= 3.3V+10%
PUMA module tested in 32 bit mode.
Output Load
I/O Pin
166Ω
1.76V
30pF
Operation Truth Table
/CS1
L
H
H
H
L
H
L
L
H
H
H
L
H
L
X
H
/CS2
H
L
H
H
L
H
L
H
L
H
H
L
H
L
X
H
/CS3
H
H
L
H
H
L
L
H
H
L
H
H
L
L
X
H
/CS4
H
H
H
L
H
L
L
H
H
H
L
H
L
L
X
H
/OE
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
X
/WE
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
Supply Current
I
CC8
I
CC8
I
CC8
I
CC8
I
CC16
I
CC16
I
CC32
I
CC8
I
CC8
I
CC8
I
CC8
I
CC16
I
CC16
I
CC32
Mode
Write D0~D7
Write D8~D15
Write D16~D23
Write D24~D31
Write D0~D15
Write D16~D31
Write D0~D31
Read D0~D7
Read D8~D15
Read D16~D23
Read D24~D31
Read D0~D15
Read D16~D31
Read D0~D31
I
CC32
/I
CC16
/I
CC8
D0~D31 High-Z
I
SB
, I
SB1
D0~D31 Standby
Notes : H=V
IH
: L=VI
L
: X=V
IH
or V
IL
PAGE 4
Issue 5.2 April 2001
Read Cycle
12
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold From Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
15
17
AC Operating Conditions
Symbol Min Max Min Max Min Max Units
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
12
-
-
-
3
3
0
0
0
-
12
12
6
-
-
-
6
6
15
-
-
-
3
3
0
0
0
-
15
15
7
-
-
-
7
7
17
-
-
-
3
3
0
0
0
-
17
17
8
-
-
-
8
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
12
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width (/OE High)
Write Pulse Width (/OE Low)
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold time from Write Time
Output Active from End of Write
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP1
t
WP2
t
WR
t
WHZ
t
DW
t
DH
t
OW
Min
12
8
8
0
8
12
0
0
6
0
3
Max
-
-
-
-
-
-
-
6
-
-
-
Min
15
10
10
0
10
12
0
0
7
0
3
15
Max
-
-
-
-
-
-
-
7
-
-
-
Min
17
12
12
0
12
13
0
0
8
0
3
17
Max
-
-
-
-
-
-
-
8
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PAGE 5
Issue 5.2 April 2001
DSP and ARM Processors
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