PDM41251
PDM41252
256K Static RAM
64K x 4-Bit
with Separate I/O
Features
s
High speed access times
Com’l: 7, 8, 10, 12 and 15 ns
Ind’l: 8, 10, 12, and 15 ns
s
Low power operation (typical)
- PDM41251sa, PDM41252SA
Active: 400 mW
Standby: 150 mW
- PDM41251la, PDM41252LA
Active: 350 mW
Standby: 25 mW
s
Separate data input and output pins
s
PDM41251: output track inputs during write
mode
s
PDM41252: high-impedance outputs during
write mode
s
TTL-compatible inputs and outputs
s
Single +5V (±10%) power supply
s
Packages
Plastic SOJ (300 mil) - TSO
Plastic TSOP - T
1
2
3
4
5
6
7
8
9
10
11
12
Description
The PDM41251 and PDM41252 are high-
performance CMOS static RAMs organized as
65,536 x 4 bits. This product is produced in
Paradigm’s proprietary CMOS technology which
offers the designer the highest speed parts. Writing
to these devices is accomplished when the write
enable (WE) and the chip enable (CE) inputs are
both LOW. Reading is accomplished when WE
remains HIGH and CE goes LOW.
The PDM41251 and PDM41252 operate from a sin-
gle +5V power supply and all the inputs and
outputs are fully TTL compatible. The PDM41251
and PDM41252 each come in two versions, the
standard power version PDM41251SA and
PDM41252SA and a low power version the
PDM41251LA and PDM41252LA. The two ver-
sions are functionally the same and only differ in
their power consumption.
The PDM41251 and PDM41252 are available in a
28-pin plastic TSOP and a 28-pin 300-mil plastic
SOJ for surface mount applications.
Functional Block Diagram
Rev 2.0 - 7/17/96
3-25
PDM41251, PDM41252
Pin Configurations
TSOP
SOJ
Pin Description
Name
A15-A0
D3-D0
Y3-Y0
WE
CE
V
CC
V
SS
Description
Address Inputs
Data Inputs
Data Outputs
Write Enable Input
Chip Enable Input
Power (+5V)
Ground
Truth Table
WE
X
H
L
L
CE
H
L
L
L
Output
Hi-Z
D
OUT
D
IN
Hi-Z
MODE
Standby
Read
Write
(2)
Write
(3)
NOTE:
1.
2.
3.
H = V
IH
, L = V
IL
, X = DON’T CARE
For PDM41251 only.
For PDM41252 only.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with Respect to V
SS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Com’l.
–0.5 to +7.0
–55 to +125
–55 to +125
1.0
50
Ind.
–0.5 to +7.0
–65 to +135
–65 to +150
1.0
50
Unit
V
°C
°C
W
mA
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RA
TINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions
Symbol
V
CC
V
SS
Commercial
Industrial
Parameter
Supply Voltage
Supply Voltage
Ambient Temperature
Ambient Temperature
Min.
4.5
0
0
–40
Typ.
5.0
0
25
25
Max.
5.5
0
70
85
Unit
V
V
°C
°C
3-26
Rev 2.0 - 7/17/96
PDM41251, PDM41252
DC Electrical Characteristics
(V
CC
= 5.0V ± 10%)
Symbol
Parameter
Test Conditions
PDM41251/2SA
Min.
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 8 mA, V
CC
= Min.
I
OL
= 10 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
V
CC
= MAX., V
IN
= V
SS
to V
CC
V
CC
= MAX.,
CE = V
IH
, V
OUT
= V
SS
to V
CC
Com’l/
Ind.
Com’l/
Ind.
–5
–5
–0.5
(1)
2.2
—
—
2.4
Max.
5
5
0.8
6.0
0.4
0.5
—
PDM41251/2LA
Min.
–5
–5
–0.5
(1)
2.2
—
—
2.4
Max.
5
5
0.8
6.0
0.4
0.5
—
µA
µA
V
V
V
V
V
Unit
1
2
3
4
NOTE: 1. V
IL
(min) = –3.0V for pulse width less than 20 ns.
Power Supply Characteristics
-7
Symbol Parameter
I
CC
Operating Current
CE = V
IL
f = f
MAX
= 1/t
RC
V
CC
= Max
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
f = f
MAX
= 1/t
RC
V
CC
= Max
I
SB1
Full Standby Current
CE
≥
V
CC
– 0.2V
f=0
V
CC
= Max
V
IN
≥
V
CC
– 0.2V or
≤
0.2V
-8
Ind.
210
190
-10
Com’l.
190
170
Ind.
200
180
-12
Com’l.
180
160
Ind.
190
170
-15
Com’l.
170
150
Ind.
180
160
Units
mA
mA
Power Com’l. Com’l.
SA
LA
210
190
200
180
5
6
7
8
9
SA
LA
SA
LA
90
90
20
5
80
80
20
5
80
80
20
10
70
70
20
5
70
70
20
10
60
60
20
5
60
60
20
10
50
50
20
5
50
50
20
10
mA
mA
mA
mA
SHADED AREA = PRELIMINARY DATA
NOTE:All values are maximum guaranteed values.
Capacitance
(1)
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Max.
8
8
Unit
pF
pF
10
11
12
NOTE:1. This parameter is determined by device characterization but is not production tested.
Rev 2.0 - 7/17/96
3-27
PDM41251, PDM41252
Read Cycle No. 1
(1)
1
2
3
Read Cycle No. 2
(2)
4
5
6
AC Electrical Characteristics
Description
READ Cycle
READ cycle time
Address access time
Chip enable access time
Output hold from address change
Chip enable to output in low Z
(3, 4, 5)
Chip disable to output in high
Z
(3, 4, 5)
Sym
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
0
7
3
5
5
0
8
-7
(6)
-8
(6)
-10
(6)
-12
-15
7
ns
15
15
ns
ns
ns
ns
10
ns
ns
15
ns
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
7
7
7
3
5
5
0
10
8
8
8
3
5
10
0
12
10
10
10
3
5
10
0
12
12
12
3
5
15
8
9
10
11
12
Chip enable to power up time
(4)
Chip disable to power down time
(4)
SHADED AREA = PRELIMINARY DATA.
Notes referenced are after Data Retention Table.
Rev 2.0 - 7/17/96
3-29
Embedded System
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