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Datasheet> All Categories > storage> storage> PDM21256LL10T
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PDM21256LL10T

Description
Standard SRAM, 32KX8, 100ns, CMOS, PDSO28
Categorystorage    storage   
File Size224KB，8 Pages
ManufacturerIXYS
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PDM21256LL10T Overview

Standard SRAM, 32KX8, 100ns, CMOS, PDSO28

PDM21256LL10T Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIXYS
Reach Compliance Codeunknown
Maximum access time100 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G28
JESD-609 codee0
memory density262144 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of terminals28
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP28,.53,22
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/SerialPARALLEL
power supply2.7 V
Certification statusNot Qualified
Maximum standby current0.000006 A
Minimum standby current1.5 V
Maximum slew rate0.025 mA
Nominal supply voltage (Vsup)2.7 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.55 mm
Terminal locationDUAL

PDM21256LL10T Preview

PRELIMINARY
PDM21256LL
32K x 8-Bit Low Power
2.7 Volt
Features
n
Description
The PDM21256LL is a very low power CMOS static
RAM organized as 32,768 x 8 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE) inputs are both LOW.
Reading is accomplished when WE remains HIGH
and CE and OE are both LOW.
The PDM21256LL operates from a single +2.7V
power supply and all the inputs and outputs are
fully TTL- compatible. The device supports low data
retention voltage for battery back-up operation with
low current.
The PDM21256LL is available in a 28-pin plastic
TSOP.
High-speed access times
Com’l: 100 and 120ns
Low power operation (typical)
- PDM21256LL
Active: 40 mW
Standby: 1µW
Single +2.7V (±0.3V) power supply
TTL-compatible inputs and outputs
I/Os are 3.6V tolerant
Low data retention voltage: 1.5V
Packages
Plastic TSOP (I) - T
n
n
n
n
n
n
Functional Block Diagram
Addresses
A
0
•
•
•
•
•
A
14
Decoder
•
•
•
•
•
•
Memory
Matrix
I/O
0
•
•
I/O
7
• • • • •
Input
Data
Control
Column I/O
•
•
CE1
WE
OE
Control
•
Rev. 0.0 - 4/03/98
1
PRELIMINARY
PDM21256LL
Pin Configurations
TSOP (I)
Pin Description
Name
Description
Address Inputs
Data Inputs/Outputs
Output Enable Input
Write Enable Input
Chip Enable Input
Power (+2.7V)
Ground
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
I/O0
A0
A1
A2
OE
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
A14-A0
I/O7-I/O0
OE
WE
CE
V
CC
V
SS
Truth Table
OE
X
L
X
H
WE
X
H
L
H
CE
H
L
L
L
I/O
Hi-Z
D
OUT
D
IN
Hi-Z
MODE
Standby
Read
Write
Output Disable
NOTE: 1. H = V
IH
, L = V
IL
, X = DON’T CARE
Absolute Maximum Ratings
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
T
j
Rating
Terminal Voltage with Respect to Vss
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Maximum Junction Temperature
(2)
Com’l.
–0.5 to +4.0
–55 to +125
–55 to +125
1.0
20
125
Ind.
–0.5 to +4.0
–65 to +135
–65 to +150
1.0
20
125
Unit
V
°C
°C
W
mA
°C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form
: T
j
= T
a
+ P *
θ
ja
where T
a
is the ambient tempera-
ture, P is average operating power and
θ
ja
the thermal resistance of the package. For
this product, use the following
θ
ja
values:
SOJ: 78
o
C/W
TSOP: 112
o
C/W
2
Rev. 0.0 - 4/03/98
PRELIMINARY
PDM21256LL
Recommended DC Operating Conditions
Symbol
V
CC
V
SS
Commercial
Parameter
Supply Voltage
Supply Voltage
Ambient Temperature
Min.
2.4
0
0
Typ.
2.7
0
25
Max.
3.0
0
70
Unit
V
V
°C
DC Electrical Characteristics
(V
CC
= 2.7V
±
0.3V)
Symbol
I
LI
I
LO
Parameter
Input Leakage Current
Output Leakage Current
Test Conditions
V
CC
= MAX., V
IN
= Vss to V
CC
V
CC
= MAX.,
CE = V
IH
, V
OUT
=
Vss to V
CC
Min.
–1
–1
Typ.
(2)
—
—
Max.
1
1
Unit
µA
µA
V
IL
V
IH
V
OL
V
OH
I
CC
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
I
OL
= 2mA, V
CC
= Min.
I
OH
= –1 mA,
V
CC
= Min.
V
CC
= MAX
CE = V
IL
I
OUT
= 0 mA
f = f
MAX
V
CC
= MAX
CE = V
IH
V
CC
= MAX
CE
≥
V
CC
-0.2V
V
IN
≥
V
CC
-0.2V
or
≤
0.2V
–0.3
(1)
2.2
—
2.2
—
—
—
—
—
—
0.8
Vcc+0.3
0.4
—
25
V
V
V
V
mA
I
SB
I
SB1
Standby Current (TTL)
Full Standby Current
(CMOS)
—
—
—
0.2
0.1
10
mA
µA
NOTE:1.V
IL
(min) = –3.0V for pulse width less than 20 ns. 2. V
CC
= 2.7V, 25C.
Rev. 0.0 - 4/03/98
3
PRELIMINARY
PDM21256LL
Data Retention Characteristics
Symbol
V
DR
Parameter
V
CC
for data retention
Test Conditions
CE
≥
V
CC
-0.2V
V
IN
≥
V
CC
-0.2V
or
≤
0.2V
CE
≥
V
CC
-0.2V
V
IN
≥
V
CC
-0.2V
or
≤
0.2V
See waveform
See waveform
Min.
1.5
Typ.
(1)
—
Max.
—
Unit
V
I
CC DR
Data retention current
—
0.2
6
µA
t
CDR
t
R
Chip deselect to data
retention time
Recovery time
0
t
RC
—
—
—
—
ns
ns
NOTE:1.V
CC
= 2.7V, 25C.
Capacitance
(1)
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Max.
6
8
Unit
pF
pF
NOTE: 1. This parameter is determined by device characterization but is not production
tested.
AC Test Conditions
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
V
SS
to 3.0V
5 ns
1.5V
1.5V
See Figures 1 and 2
4
Rev. 0.0 - 4/03/98
PRELIMINARY
PDM21256LL
+2.7V
+2.7V
319Ω
DATA
OUT
353Ω
100 pF
DATA
OUT
353Ω
319Ω
5 pF
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
, t
LZOE
, t
HZOE
)
Low V
CC
Data Retention Waveform
Data Retention Mode
V CC
2.7V
VDR
2.7V
t
CDR
VIH
V IL
VDR
t
RC
CE
DON'T CARE
Rev. 0.0 - 4/03/98
5
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PDM21256LL10T Related Products

PDM21256LL10T PDM21256LL12T
Description Standard SRAM, 32KX8, 100ns, CMOS, PDSO28 Standard SRAM, 32KX8, 120ns, CMOS, PDSO28
Is it Rohs certified? incompatible incompatible
Maker IXYS IXYS
Reach Compliance Code unknown unknow
Maximum access time 100 ns 120 ns
I/O type COMMON COMMON
JESD-30 code R-PDSO-G28 R-PDSO-G28
JESD-609 code e0 e0
memory density 262144 bit 262144 bi
Memory IC Type STANDARD SRAM STANDARD SRAM
memory width 8 8
Number of terminals 28 28
word count 32768 words 32768 words
character code 32000 32000
Operating mode ASYNCHRONOUS ASYNCHRONOUS
Maximum operating temperature 70 °C 70 °C
organize 32KX8 32KX8
Output characteristics 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Encapsulate equivalent code TSSOP28,.53,22 TSSOP28,.53,22
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/Serial PARALLEL PARALLEL
power supply 2.7 V 2.7 V
Certification status Not Qualified Not Qualified
Maximum standby current 0.000006 A 0.000006 A
Minimum standby current 1.5 V 1.5 V
Maximum slew rate 0.025 mA 0.025 mA
Nominal supply voltage (Vsup) 2.7 V 2.7 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form GULL WING GULL WING
Terminal pitch 0.55 mm 0.55 mm
Terminal location DUAL DUAL

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